AN2018S Datasheet, PDF (1/3 Pages) Panasonic Semiconductor – Correlated Double Sampling IC

AN2018S
Correlated Double Sampling IC
s Overview
The AN2018S is used to reduce noise in CCD im-
age sensor output signal. It performs correlated double-
sampling on image signal sent from a CCD sensor to
output clearer image signal.
s Features
• Operating on low voltage (VCC=4.8V), consuming
little current (ICC=12.7mA typ.)
• Including a high-speed sampling circuit responding
to 510-830H CCD
• 6dB or 9dB fixed gain
• 83-dB high S/N-ratio (at 6dB output)
Unit:mm
0.3
4.2±0.3
6.5±0.3
8-Pin SOP Package (SOP008-P-0225)
s Pin Descrpiptions
Pin No.
Pin name
1 CDS output (9dB)
2 Blanking pulse input
3 CCD signal input
4 VCC
5 Sampling pulse input (2)
6 Sampling pulse input (1)
7 GND
8 CDS output (6dB)
s Block Diagram
6dB OUT
GND
SP1
SP2
8
7
6
5
+
9dB
–
BLK
50kΩ
BIAS
1
9dB OUT
2
BLK
+
6dB
–
S/H
S/H
3
4
SIG.IN
VCC