PAM3102 Datasheet, PDF (9/11 Pages) Power Analog Micoelectronics – Dual 150mA High PSRR Low-Dropout CMOS Regulator

PAM3102
Dual 150mA High PSRR Low-Dropout CMOS Regulator
Application Information
Capacitor Selection and Regulator Stability
Similar to any low dropout regulator, the external
capacitors used with the PAM3102 must be
carefully selected for regulator stability and
performance.
A capacitor C_IN of more than 1μF can be
employed in the input pin, while there is no upper
limit for the capacitance of C ._IN Please note that
the distance between C_IN and the input pin of the
PAM3102 should not exceed 0.5 inch. Ceramic
capacitors are suitable for the PAM3102.
Capacitors with larger values and lower ESR
(equivalent series resistance) provide better
PSRR and line-transient response.
The PAM3102 is designed specifically to work
with low ESR ceramic output capacitors in order
to save space and improve performance. Using
an output ceramic capacitor whose value is
>2.2μF with ESR>5mΩ ensures stability.
Shutdown Input Operation
The PAM3102 is shutdown by pulling the CE
input low, and turned on by tying the CE input to
VIN or leaving the CE input floating.
Input-Output ( Dropout ) Voltage
A regulator's minimum input-output voltage
differential (or dropout voltage) determines the
lowest usable supply voltage. The PAM3102 has
a typical 180mV dropout voltage. In battery-
powered systems, this will determine the useful
end-of-life battery voltage.
Current Limit and Short Circuit Protection
The PAM3102 features a current limit, which
monitors and controls the gate voltage of the
pass transistor. The output current can be limited
to 300mA by regulating the gate voltage. The
PAM3102 also has a built-in short circuit
current limit.
Thermal considerations
Thermal protection limits power dissipation in the
PAM3102. When the junction temperature
exceeds 150°C, the OTP (Over Temperature
Protection) starts the thermal shutdown and
turns the pass transistor off. The pass transistor
resumes operation after the junction temperature
drops below 120°C.
For continuous operation, the junction
temperature should be maintained below 125°C.
The power dissipation is defined as:
P_D= (V -_IN V_O)*I_O+Vin*Ignd
The maximum power dissipation depends on the
thermal resistance of IC package, PCB layout,
the rate of surrounding airflow and temperature
difference between junction and ambient. The
maximum power dissipation can be calculated by
the following formula:
P_D(MAX) = (T - _J(MAX) T_A)/θ_JA
Where T_J(MAX) is the maximum allowable junction
temperature 125°C,T_A is the ambient
temperature and θ_JA is the thermal resistance
from the junction to the ambient.
For example, as θ_JA is 250°C/W for the SOT-23
package based on the standard JEDEC 51-3 for
a single-layer thermal test board, the maximum
power dissipation at TA =25°C can be calculated
by following formula:
P_D(MAX)=(125°C-25°C)/250=0.4W SOT-23
It is also useful to calculate the junction
temperature of the PAM3102 under a set of
specific conditions. Suppose the input voltage
V = _IN 3.3V, the output current I_O=300mA and the
case temperature T_A=40°C measured by a
thermalcouple during operation, the our power
dissipation is defined as:
P_D=(3.3V-2.8V)*150mA+(3.3V-1.8V)
*150mA+3.3V*200μA≌300mW
And the junction temperature T_J can be
calculated as follows:
T_J = T_A+P_D*θ_JA
T_J= 40°C+0.3W*250°C/W
=40°C+75°C
=115°C<T_J(MAX) = 125°C
For this application, T_J is lower than the absolute
maximum operating junction temperature,125°C,
so it is safe to use the PAM3102 in this
configuration.
Power Analog Microelectronics,Inc
www.poweranalog.com
9
09/2008 Rev 1.1