UHP112 Datasheet, PDF (5/8 Pages) Oxford Semiconductor – Two-Port PCI-to-USB OpenHCI Host Controller - Product Brief

UHP112
Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions
Pin Symbol*
Type
Description
1
A20MN Output/Open Drain Legacy Gate A20 Output (Active-Low).
2
AD2
Bidir
PCI Address/Data Bit.
3
AD1
Bidir
PCI Address/Data Bit.
4
AD0
Bidir
PCI Address/Data Bit.
5
VSS
Power
Device Ground.
6
CLK48
Input
USB Clock (48 MHz).
7
VDD
Power
Device Power (3.3 V).
8
PMEN Output/Open Drain Power Management Event (Active-Low).
9 PRTPWR1
Bidir
Port 1 Power. Logic output expected to turn on port 1 power. Boot-
strap low for high active. Bootstrap high for low active.
10 PWRFLT1N
Input
Port 1 Power Fault (Active-Low). Logic input indicates an overcur-
rent fault on port 1.
11 PWROK1
Input
Port 1 Power OK. Analog or digital input to inform the UHP112 that
USB port 1 power is stable (when >4 V).
12
VDDT
Power
Transceiver Power (3.3 V).
13
DPLS1
Bidir
DIfferential USB Port 1 Signals.
14
DMNS1
Bidir
15 PMIENABLE
Input
Power Management Interface Enable Input (Active-High).
16
VSST
Power
Transceiver Ground.
17
VDDT
Power
Transceiver Power (3.3 V).
18
DPLS2
Bidir
Differential USB Port 2 Signals.
19
DMNS2
Bidir
20
VSS
Power
Device Ground.
21
TEST0
Input
Test 0. For device testing. Connect this to ground during normal use.
Connect to logic high for NAND tree mode. See NAND Tree Mode
on page 2-32.
22 PWROK2
Input
Port 2 Power OK. Analog or digital input to inform the UHP112 that
USB port 2 power is stable (when >4 V).
23 PWRFLT2N
Input
Port 2 Power Fault (Active-Low). Logic input indicates an overcur-
rent fault on port 2.
24 PRTPWR2
Bidir
Port 2 Power. Logic output expected to turn on port 2 power. Boot-
strap low for high active. Bootstrap high for low active.
25
TEST1
Input
Test 1. For device testing. Tie this to ground during normal use.
Connect to logic high for NAND tree mode. See the NAND Tree
Mode section on page 2-32.
26
VDD5
Power
5 V Power for 5 V PCI Operation. 5 V must be present on this pin
while selecting either 3 V PCI or 5 V PCI operation with the VIO pin.
See PCI Connection Instructions section on page 2-26.
27
IRQ1
Output/Open Drain System Keyboard Interrupt (Active-High).
28
IRQ12 Output/Open Drain System Mouse Interrupt (Active-High).
29
SMIN
Output/Open Drain System Management Interrupt (Active-Low).
30
INTAN Output/Open Drain PCI Interrupt (Active-Low).
31
RSTN
Input
PCI Reset (Active-Low). Also the chip reset.
32
CLK
Input
PCI Clock. 33 MHz input clock.
* Active-low signals within this document are indicated by an N following the symbol names.
Transdimension Inc.
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