PDSP2110 Datasheet, PDF (10/14 Pages) OSRAM GmbH – Lead (Pb) Free Product - RoHS Compliant

PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Data Input Commands
Signals
CE
WR FL
A3
A2
A1
A0
1
X
X
X
X
X
X
X
1
X
X
X
X
X
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
X
0
0
0
0
0
0
X
0
0
1
0
0
0
X
0
1
0
0
0
0
X
1
1
1
0
0
0
X
1
0
0
0
0
0
X
1
0
1
0
0
0
X
1
1
0
0
0
0
X
1
1
1
X=Don’t care
Operation
No operation
No operation
Write Control Register
Digit 0 (left)
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7 (right)
Digit 0 (left)
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7 (right)
Write display data to
user RAM and Page
Select Register
D0–D6=ASCII Data
D7=0 Select ROM 1
D7=1 Select ROM 2
Write Flash RAM Register
D0=0 Flashing Charac. off
D0=1 Flashing Charac. on
D1–D7=X
Power up Sequence
Upon power up display will come on at random. Thus the display
should be reset on power-up. The reset will clear the Flash RAM,
Control Word Register and reset the internal counter. All the dig-
its will show blanks and display brightness level will be 100%.
Microprocessor Interface
The interface to a microprocessor is through the 8-bit data bus
(D0-D7), the 4-bit address bus (A0-A3) and control lines FL, CE
and WR.
To write data (ASCII/ Control Word) into the display CE should be
held low, address and data signals stable and WR should be
brought low.
The Control Word is decoded by the Control Word Decode Logic.
Each code has a different function. The code for display brightness
changes the duty cycle for the column drivers. The peak LED cur-
rent stays the same but the average LED current diminishes
depending on the intensity level.
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with column drive signal and makes the col-
umn driver to cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby making
all eight digits to blink at 2.0 Hz.
The Lamp Test causes the column drivers to run at 1/2 duty cycle
thus all the LEDs in all eight digits turn on at 50% intensity.
Clear bit clears the character RAM and writes a blank into the dis-
play memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display at
this point. For multiple display operation, CLK I/O must be properly
selected. CLK I/O will output the internal clock if CLKSEL=1, or will
allow input from an external clock if CLKSEL=0.
2006-01-23
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