NCP3020A Datasheet, PDF (9/23 Pages) ON Semiconductor – Synchronous PWM Controller

NCP3020A, NCP3020B
DETAILED DESCRIPTION
OVERVIEW
The NCP3020A/B operates as a 300/600 kHz, voltage
mode, pulse width modulated, (PWM) synchronous buck
converter. It drives high−side and low−side N−channel power
MOSFETs. The NCP3020 incorporates an internal boost
circuit consisting of a boost clamp and boost diode to provide
supply voltage for the high side MOSFET gate driver. The
NCP3020 also integrates several protection features including
input undervoltage lockout (UVLO), output undervoltage
(OUV), output overvoltage (OOV), adjustable high−side
current limit (I_SET and I_LIM), and thermal shutdown (TSD).
The operational transconductance amplifier (OTA)
provides a high gain error signal from Vout which is
compared to the internal 1.5 V pk-pk ramp signal to set the
duty cycle converter using the PWM comparator. The high
side switch is turned on by the positive edge of the clock
cycle going into the PWM comparator and flip flop
following a non-overlap time. The high side switch is turned
off when the PWM comparator output is tripped by the
modulator ramp signal reaching a threshold level
established by the error amplifier. The gate driver stage
incorporates symmetrical fixed non− overlap time between
the high−side and low−side MOSFET gate drives to prevent
cross conduction of the power MOSFET’s.
POR and UVLO
The device contains an internal Power On Reset (POR) and
input Undervoltage Lockout (UVLO) that inhibits the internal
logic and the output stage from operating until V_CC reaches its
respective predefined voltage levels (4.3 V typical).
Startup and Shutdown
Once enable is asserted the device begins its startup
process. Closed−loop soft−start begins after a 400 ms delay
wherein the boost capacitor is charged, and the current limit
threshold is set. During the 400 ms delay the OTA output is
set to 700 mV which is just below the low point of the
internal ramp. This is done to reduce delays and to ensure a
consistent pre−soft−start condition. The device increases the
internal reference from 0 V to 0.6 V in 32 discrete steps
while maintaining closed loop regulation at each step. Some
overshoot may be evident at the start of each step depending
on the voltage loop phase margin and bandwidth. See
Figure 21. The total soft−start time is 6.8 ms for the
NCP3020A and 3.4 ms for the NCP3020B.
0.6 V Output Voltage
18.75 mV Steps
32 Voltage Steps
Internal Reference Voltage
Internal Ramp
OTA Output
0 .7V
0V
Output Voltage
Internal Reference Voltage
0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 22 2 2 2 2 3 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 45 6 7 8 9 0 1 2
Switch
Node
OTA Output
Figure 21. Soft−Start Details
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