NCN5130 Datasheet, PDF (9/58 Pages) ON Semiconductor – Transceiver

NCN5130
Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions
unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min
Typ
Max Unit
FAN−IN CONTROL
I_pu,fanin
FANIN
DIGITAL INPUTS
Pull−Up Current FANIN−pin
FANIN shorted to GND,
Pull−up connected to V_AUX
10
20
40
mA
V_IL
V_IH
R_DOWN
SCK/UC2,
SDI/RXD,
CSB/UC1,
TREQ,
MODE1,
MODE2,
XSEL,
XCLKC,
XTAL2
Logic Low Threshold
Logic High Threshold
Internal Pull−Down Resistor
0
2.65
SCK/UC2−, SDI/RXD− and
CSB/UC1 pin excluded. Only valid
5
in Normal State.
0.7
V
V_DDD
V
10
28
kW
DIGITAL OUTPUTS
V_OL
SCK/UC2, Logic low output level
SDO/TXD,
V_OH
CSB/UC1, _{Logic high output level}
XCLK,TRIG
SCK/UC2,
XCLK,TRIG
I_L
Load Current
SDO/TXD,
CSB/UC1
0
V_DDD −
0.45
0.4
V
V_DDD
V
8
mA
4
mA
V_OL
SAVEB,
R_up
RESETB
ANALOG OUTPUT
Logic low level open drain
Internal Pull−up Resistor
I_OL = 4 mA
0.4
V
20
40
80
kW
PV_BUS
PV_FILT
PV_20V
PV_DDA
PV_DD2
PI_BUS
PT_J
VTJ_OFF
V_OFF
t_SW,ANA
ANAOUT
Analog output division ratio for V_BUS
Analog output division ratio for V_FILT
Analog output division ratio for V_20V
Analog output division ratio for V_DDA
Analog output division ratio for V_DD2MV
Analog output conversion ratio for I_BUS
Analog output conversion ratio for T_junction
Analog output offset for T_junction at 300K
Analog output offset voltage
Time between writing Analog Control Register 1 and stable ANAOUT
voltage (<1 nF capacitive load)
0.067
0.071
0.086
0.438
0.950
14.0
−12
0.071
0.075
0.091
0.462
1.000
20.9
−4
1.309
33
0.075
0.079
0.096
0.485
1.050
28.8
12
V/A
mV/K
V
mV
ms
TEMPERATURE MONITOR
T_TW
Thermal Warning
T_TSD
Thermal shutdown
T_Hyst
Thermal Hysteresis
DT
Delta T_TSD and T_TW
PACKAGE THERMAL RESISTANCE VALUE
Rising temperature (See Figure 8) 105
115
125
°C
Rising temperature (See Figure 8) 130
140
150
°C
See Figure 8
5
11
15
°C
See Figure 8
21.7
°C
R_q,_ja
Thermal Resistance
Junction−to−Ambient
Simulated Conform
JEDEC JESD−51, (2S2P)
Simulated Conform
JEDEC JESD−51, (1S0P)
30
K/W
60
K/W
R_q,_jp
Thermal Resistance
Junction−to−Exposed Pad
0.95
K/W
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