LC72720YV Datasheet, PDF (9/18 Pages) Sanyo Semicon Device – Single-Chip RDS Signal-Processing System IC

LC72720YV
CCB Input data format
[1] CCB address 6A
IN1 data, first bit
BB B B A AA A
FF FF S O EEE EEC
DI
01 2 3 0 12 3
B
SS SS Y WCCC
S
CC T
0123 R E 012 340
01 0 1 0 11 0
(11) Circuit control
(5) Error correction method setting
(4) RAM write control
(3) Synchronization and RAM address reset
(2) Synchronization detection method setting
(1) Synchronization protection method setting
[2] CCB address 6B
IN2 data, first bit
BBB B AAA A
C
DI
012 3 012 3
T
1
110 1 011 0
PP PPP
X
R
L L TTT
S
M
01 012
TTTT
SSSS
0123
Caution : The bits labeled with an asterisk must be set to 0.
(10) Test mode settings
(9) Output pin settings
(8) RDS/RBDS selection
(7) Demodulation circuit phase control
(6) Crystal oscillator frequency selection
(11) Circuit control
(1) Synchronization protection (forward protection) method setting (4bits) : FS0 to FS3
FS3 = 0 : If offset words in the correct order could not be detected continuously during the number of blocks
specified by FS0 to FS2, take that to be a lost synchronization sate.
FS3 = 1 : If blocks with uncorrectable errors were received consecutively during the number of blocks specified by
FS0 to FS2, take that to be a lost synchronization state.
FFF
SSS
012
000
100
010
110
001
101
011
111
Condition for detecting lost synchronization
If 3 consecutive blocks matching the FS3 condition are received.
If 4 consecutive blocks matching the FS3 condition are received.
If 5 consecutive blocks matching the FS3 condition are received.
If 6 consecutive blocks matching the FS3 condition are received.
If 8 consecutive blocks matching the FS3 condition are received.
If 10 consecutive blocks matching the FS3 condition are received.
If 12 consecutive blocks matching the FS3 condition are received.
If 16 consecutive blocks matching the FS3 condition are received.
Initial value : FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0
No. 6488-9/18