LC709004A Datasheet, PDF (9/13 Pages) ON Semiconductor – I/O-Expander for Microcontroller

LC709004A
(2) Data communication mode
1) When the CS pin is set low with the RES pin held high, the LC709004A gets ready for serial communication.
(Subsequently, processing in steps 2) and 3) are identical to steps 2) and 3) in paragraph (1)-2).
2) The input data at P00 is sent directly to the DOUT pin on the first falling edge of the CLK signal. Data at pins
P01 to P17 is loaded into the shift register on the next rising edge of the clock.
3) Subsequently, the ports' input data, which is loaded into the shift register on the falling edge of CLK, is placed at
the DOUT pin sequentially (P00→P07, P10→P17) in synchronization with the falling edges of CLK, starting at
port pin P00. In parallel with this operation, when data to be placed at the ports is supplied to the DIN pin
sequentially starting at the port pin P00 (P00→P07, P10→P17), it is loaded into the internal shift register in
synchronization with the rising edges of CLK.
4) When the CS pin is set high after the rising edge of the 16th clock, the data loaded in the shift register is loaded
into the DDR register which determines the output state of the ports and the states of all port pins (P00 to P17) are
then changed (output) according to the conditions established in the DDR and DTR registers. Serial data that
occurs following the initial communication mode processing is always loaded into the DTR register.
RES
CS
CLK
0
1
2
3
4
5
6
7
8
9 14 15
DIN
P00_DO P01_DO P02_DO P03_DO P04_DO P05_DO P06_DO P07_DO P10_DO P11_DO P16_DO P17_DO
DOUT P27_DI(Previous Data) P00_DI P01_DI P02_DI P03_DI P04_DI P05_DI P06_DI P07_DI P10_DI P11_DI P16_DI
P17_DI
DDR
DTR
P00 to P17
Hi-Z
Hi-Z
P00-P17_OUT
* PXX_DO denotes the output data to the port pin identified by PXX.
Fig. 3
5) Subsequently, the state of all port pins (P00 to P17) is updated each time the set of steps 1) to 4) described in
paragraph (2) are performed.
RES
CS
CLK
0
1
2
3
4
5
6
7
8
9 14 15
DIN
P00_DO P01_DO P02_DO P03_DO P04_DO P05_DO P06_DO P07_DO P10_DO P11_DO P16_DO P17_DO
DOUT P17_DI(Previous Data) P00_DI P01_DI P02_DI P03_DI P04_DI P05_DI P06_DI P07_DI P10_DI P11_DI P16_DI
P17_DI
DDR
DTR
P00 to P17
P00-P17_OUT (Previous Data)
P00-P17_OUT (Previous Data) P00-P17_OUT
Fig. 4
No.A0165-9/13