KAF-4301 Datasheet, PDF (9/25 Pages) ON Semiconductor – FULL FRAME CCD IMAGE SENSOR

KAF-4301 Image Sensor
Pin Name
1 φV2
2 φV2
3 φV1
4 φV1
5 VSUB
6 N/C
7 N/C
8 N/C
9 VGUARD
10 VSUB
11 VDD2
12 VOUT2
13 VLG
14 VSS
15 VRD
16 φR
17 VDD1
18 VOUT1
19 VOG
20 VSUB
Description
Vertical (Parallel) CCD Clock - Phase 2
Vertical (Parallel) CCD Clock - Phase 2
Vertical (Parallel) CCD Clock - Phase 1
Vertical (Parallel) CCD Clock - Phase 1
Substrate
No Connection
No Connection
No Connection
Guard Ring
Substrate
High Sensitivity Two-Stage Amplifier Supply
Video Output from High Sensitivity Two-Stage Amplifier
First Stage Load Transistor Gate for Two-Stage Amplifier
High Sensitivity Two-Stage Amplifier Return
Reset Drain
Reset Clock
High Dynamic Range Single-Stage Amplifier Supply
Video Output from High Dynamic Range Single-Stage
Amplifier
Output Gate
Substrate
Pin Name
40 φV2
39 φV2
38 φV1
37 φV1
36 VSUB
35 N/C
34 N/C
33 N/C
32 N/C
31 N/C
30 VGUARD
29 VSUB
28 φV1
27 φV2
26 φH1
25 φH2
24 φH22
23 φH21
22 VGUARD
21 VSUB
Description
Vertical (Parallel) CCD Clock - Phase 2
Vertical (Parallel) CCD Clock - Phase 2
Vertical (Parallel) CCD Clock - Phase 1
Vertical (Parallel) CCD Clock - Phase 1
Substrate
No Connection
No Connection
No Connection
Guard Ring
Substrate
Vertical (Parallel) CCD Clock - Phase 1
Vertical (Parallel) CCD Clock - Phase 2
Horizontal (Serial) CCD Clock - Phase 2
Horizontal (Serial) CCD Clock - Phase 1
Last Horizontal (Serial) CCD Phase - Split
Gate
Last Horizontal (Serial) CCD Phase - Split
Gate
Guard Ring
Substrate
Notes:
1.
2.
3.
4.
Pins 1, 2, 27, 39 and 40 must be connected together - only one Phase 2-clock driver is required.
Pins 3, 4, 28, 37 and 38 must be connected together - only one Phase 1-clock driver is required.
Pins 5, 10, 20, 21, 29 and 36 should be connected to a common potential.
Pins 9, 22 and 30 should be connected to a common potential.
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Revision 2.1 PS-0038Pg9