AMIS-42770_14 Datasheet, PDF (9/13 Pages) ON Semiconductor – Dual High Speed CAN Transceiver

AMIS−42770
Table 6. DC AND TIMING CHARACTERISTICS
(V_CC = 4.75 to 5.25 V; T_junc = −40 to +150°C; R_LT = 60 W unless specified otherwise.)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
BUS LINES (pins CANH1/2 and CANL1/2)
V_i(dif)(th)
Differential receiver threshold
−5 V < V_CANLx < +12 V;
0.5
voltage
−5 V < V_CANHx < +12 V;
see Figure 7
0.7
0.9
V
V_{ihcm(dif) (th)}
Differential receiver threshold
−35 V < V_CANLx < +35 V;
0.3
voltage for high common−
−35 V < V_CANHx < +35 V;
mode
see Figure 7
0.7
1.05
V
V_{i(dif) (hys)}
Differential receiver input volt-
−35 V < V_CANL < +35 V;
50
age hysteresis
−35 V < V_CANH < +35 V;
see Figure 7
70
100
mV
R_i(cm)(CANHx)
Common−mode input resist-
ance at pin CANH1/2
15
26
37
KW
R_{i(cm) (CANLx)}
Common−mode input resist-
ance at pin CANL1/2
15
26
37
KW
R_i(cm)(m)
Matching between pin CANH1/2
V_CANHx = V_CANLx
−3
and pin CANL1/2 common−
mode input resistance
0
+3
%
R_i(dif)
Differential input resistance
25
C_i(CANHx)
Input capacitance at pin
CANH1/2
V_Tx0 = V_CC; not tested
50
75
KW
7.5
20
pF
C_i(CANLx)
Input capacitance at pin
CANL1/2
V_Tx0 = V_CC; not tested
7.5
20
pF
C_i(dif)
I_LI(CANHx)
I_LI(CANLx)
V_CM−peak
Differential input capacitance
Input leakage current at pin
CANH1/2
Input leakage current at pin
CANL1/2
Common−mode peak during
transition from dom → rec or
rec → dom
V_Tx0 = V_CC; not tested
V_CC < PORL_VCC;
−5.25 V < V_CANHx < 5.25 V
V_CC < PORL_VCC;
−5.25 V < V_CANLx < 5.25 V
See Figure 11
−350
−350
−1000
3.75
170
170
10
pF
350
mA
350
mA
1000
mV
V_CM−step
Difference in common−mode
between dominant and recess-
ive state
See Figure 11
−250
250
mV
THERMAL SHUTDOWN
T_j(sd)
Shutdown junction temperature
150
°C
TIMING CHARACTERISTICS (see Figures 8 and 9)
t_{d(Tx−BUSon)}
t_{d(Tx−BUSoff)}
t_{d(BUSon−RX)}
t_{d(BUSoff−RX)}
t_d(ENxB)
Delay Tx0/Text to bus active
Delay Tx0/Text to bus inactive
Delay bus active to Rx0/Rint
Delay bus inactive to Rx0/Rint
Delay from EN1B to bus act-
ive/inactive
40
85
120
ns
30
60
115
ns
25
55
115
ns
65
100
145
ns
100
200
ns
t_{d(Tx−Rx)}
Delay from Tx0 to Rx0/Rint
15 pF on the digital output
4
and from Text to Rx0
(direct logical path)
10
35
ns
t_dom
Time out counter interval
15
25
45
ms
t_d(FBS)
Delay for feedback suppres-
sion release
5+
t_{d(BUSon−RX)}
300
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
http://onsemi.com
9