PACSZ1284 Datasheet, PDF (8/11 Pages) California Micro Devices Corp – P/ACTIVE IEEE 1284 ECP/EPP TERMINATION NETWORK

PACSZ1284
Interfacing to IEEE 1284 Connectors
IEEE 1284 defines three interface connectors:
• 1284 A is a 25-pin DB series connector which is the de facto PC standard for the host connection.
• 1284 B is a 36-pin, 0.085 inch centerline connector used on the peripheral device.
• 1284 C is a new 36-pin, 0.050 inch centerline connector which can be used for both host and peripheral.
Figure 3A shows a possible hook-up between the 1284-A connector on a PC motherboard and the
PACSZ1284, illustrating how the pin configuration of the PACSZ1284 allows for easy interconnect between the
two. The dotted I/O signals of the PACSZ1284 will typically be connected to a Super I/O chip on the
motherboard.
Figure 3B shows a possible hook-up between the 1284-B connector on a peripheral and the PACSZ1284.
Figure 3C shows a possible hook-up between the 1284-C connector and the PACSZ1284.
Figure 3. Example Connections of IEEE 1284 Connectors with PACSZ1284
Table 2 provides the IEEE 1284 signal assignments for the three connectors, and example PACSZ1284 pin
connections.
When connecting a 1284-A host to a 1284-B peripheral, the “Peripheral Logic High” signal is not used.
Similarly, when a 1284-A host is connected to a 1284-C peripheral, the “Peripheral Logic High” and “Host Logic
High” are not used. These two signals are optionally used to detect a “Power Off” or “Cable Disconnect” state
for host and peripheral, respectively.
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