N84C163 Datasheet, PDF (8/11 Pages) ON Semiconductor – Supervisory Circuits with I2C Serial CMOS EEPROM Precision Reset Controller

N84C163
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8−bit address
that is to be written into the address pointers of the N84C163.
After receiving another acknowledge from the Slave, the
Master device transmits the data to be written into the
addressed memory location. The N84C163 acknowledges
once more and the Master generates the STOP condition. At
this time, the device begins an internal programming cycle
to non−volatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.
Page Write
The N84C163 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to 15
additional bytes. After each byte has been transmitted, the
N84C163 will respond with an acknowledge and internally
increment the lower order address bits by one. The high
order bits remain unchanged.
If the Master transmits more than 16 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
N84C163 in a single write cycle.
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
Figure 7. Byte Write Timing
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
A
A
A
C
C
C
K
K
K
Figure 8. Page Write Timing
DATA n + 1
A
C
K
S
T
DATA n+15 ^O
P
P
A
C
K
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
N84C163 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the N84C163 is still busy with the write
operation, no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can then
proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent memory array programming. If the WP
pin is tied to VCC, the entire memory array is protected and
becomes read only. The N84C163 will accept both slave and
byte addresses, but the memory location accessed is
protected from programming by the device’s failure to send
an acknowledge after the first byte of data is received.
www.onsemi.com
8