MC33364 Datasheet, PDF (8/16 Pages) ON Semiconductor – Critical Conduction GreenLine SMPS Controller

MC33364
Current Sense and Feedback Regulation
Current--mode control is implemented with the Current
Sense (CS) pin and Feedback (FB) pin. The FB pin is
internally pulled up with a 5 kOhm resistor from the 5 V
V_ref. There is a resistor divider circuit and a 0.1 V offset in
this functional block. The following equation describes the
relation between the voltages of the FB and CS pins, V_FB
and V_CS respectively.
VCS(max) = VFB∕4 − 0.1 V
When the output is short circuited, there is no feedback
signal from the opto coupler and the FB pin is opened. It
gives V_FB = 5 V and the maximum voltage of the CS pin is
1.15 V. When the voltage exceeds 1.15 V, the current sense
comparator turns on and terminates the MOSFET
conduction. It stops current flowing through the sense
resistor (R_Sense) and hence the sense resistor limits the
maximum MOSFET drain current by the following
equation.
Maximum Drain Current = 1.15∕Rsense
When the output voltage is too high, the FB pin voltage is
pulled down by the opto coupler current and the duty ratio
is reduced. The output voltage is then regulated.
There is a Leading Edge Blanking (LEB) circuit with
250 ns propagation delay to prevent false triggering due to
parasitics in the CS pin. It makes a minimum on--time of the
MOSFET (t_on(min)).
Thermal Shutdown
There is a thermal shutdown block to prevent overheating
condition and protect the device from overheating. When
temperature is over 180_C, the Drive output and startup
circuit block are disable. The device resumes operation
when temperature falls below 130_C.
Gate Drive Output
The IC contains a CMOS output driver specifically
designed for direct drive of power MOSFET. The Drive
Output typical rise and fall times are 50 ns with a 1.0 nF
load. Unbalanced Source and Sink eliminates the need for an
external resistor between the device Drive output and the
Gate of the external MOSFET. Additional internal circuitry
has been added to keep the Drive Output in a sinking mode
whenever the UVLO is active. This characteristic eliminates
the need for an external gate pull--down resistor.
Frequency Clamp Options
The drawback of critical conduction mode is variable
switching frequency. The switching frequency can increase
dramatically to hundreds of kHz when the output current is
too low or vanishes. It is a big problem when EMI above
150 kHz is concerned. Frequency Clamp (FC) is an optional
feature in the device to limit the upper switching frequency
to nominal 126 kHz by inserting a minimum off--time
(t_off(min)). When a minimum off--time is inserted, the
maximum frequency (f_max) limit is set.
f
max
=
ton(min)
1
+
toff(min)
The SMPS is forced to operate in DCM when the
maximum frequency is reached. The minimum off--time is
immediately counted after the driving signal goes low. If the
ZCD signal comes within this minimum off--time, the ZCD
information is ignored until the minimum off--time expires.
The next ZCD signal starts the MOSFET conduction.
There are three available FC options: MC33364D --
adjustable minimum off--time by external resistor,
MC33364D1 -- 6.9 us fixed minimum off--time, and
MC33364D2 -- no minimum off--time (FC disable).
The MC33364D has a FC pin, which can vary the
minimum off--time (or the maximum frequency) externally
in Figure 11. If the FC pin is opened, the minimum off--time
is fixed at 6.9 us. If the FC pin is grounded, the clamp is
disabled, and the SMPS will always operate in critical mode.
It is generally not recommended to sink or source more than
80 uA from the FC pin because high currents may cause
unstable operation.
Vref
FC
FC
Increase toff
FC
GND
Decrease toff
FC
toff = 6.9us
GND
toff = 0us
(FC disable)
Figure 11. Frequency Clamp Setting
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