MAX1617 Datasheet, PDF (8/12 Pages) ON Semiconductor – SMBus Temperature Sensor with Internal and External Diode Input

MAX1617
Serial Port Operation
The Serial Clock input (SCL) and bi–directional data port
(SDA) form a 2–wire bi–directional serial port for
programming and interrogating the MAX1617. The
following conventions are used in this bus architecture. (See
SMBus Write/Read Timing Diagram.)
All transfers take place under control of a host, usually a
CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The MAX1617
always operates as a slave. The serial protocol is illustrated
in Figure 3. All data transfers have two phases; all bytes are
transferred MSB first. Accesses are initiated by a start
condition (START), followed by a device address byte and
one or more data bytes. The device address byte includes a
Read/Write selection bit. Each access must be terminated by
a Stop Condition (STOP). A convention called
Acknowledge (ACK) confirms receipt of each byte. Note
that SDA can change only during periods when SCL is LOW
(SDA changes while SCL is High are reserved for Start and
Stop conditions.)
MAX1617 Serial Bus Conventions
Term Explanation
Transmitter The device sending data to the bus.
Receiver The device receiving data from the bus.
Master
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP).
Slave The device addressed by the master.
Start
A unique condition signaling the beginning
of a transfer indicated by SDA falling (High
— Low) while SCL is high.
Stop
A unique condition signaling the end of a
transfer indicated by SDA rising (Low —
High) while SCL is high.
ACK
A receiver acknowledges the receipt of
each byte with this unique condition. The
receiver drives SDA low during SCL high
of the ACK clock–pulse. The Master pro-
vides the clock pulse for the ACK cycle.
Busy
Communication is not possible because
the bus is in use.
NOT Busy When the bus is idle, both SDA and SCL
will remain high.
Data Valid
The state of SDA must remain stable dur-
ing the High period of SCL in order for a
data bit to be considered valid. SDA only
changes state while SCL is low during nor-
mal data transfers (see Start and Stop
conditions).
Start Condition (START)
The MAX1617 continuously monitors the SDA and SCL
lines for a start condition (a High to Low transition of SDA
while SCL is High), and will not respond until this condition
is met. (See SMBus Write/Read Timing Diagram.)
Address Byte
Immediately following the Start Condition, the host must
transmit the address byte to the MAX1617. The states of
ADD1 and ADD0 during power–up determine the 7–bit
SMBus address for the MAX1617. The 7–bit address
transmitted in the serial bit stream must match for the
MAX1617 to respond with an Acknowledge (indicating the
MAX1617 is on the bus and ready to accept data). The eighth
bit in the Address Byte is a Read–Write Bit. This bit is 1 for
a read operation or 0 for a write operation.
Acknowledge (ACK)
Acknowledge (ACK) provides a positive handshake
between the host and the MAX1617. The host releases SDA
after transmitting eight bits, then generates a ninth clock
cycle to allow the MAX1617 to pull the SDA line Low to
acknowledge that it successfully received the previous eight
bits of data or address.
Data Byte
After a successful ACK of the address byte, the host must
transmit the data byte to be written or clock out the data to
be read. (See the appropriate timing diagrams.) ACK will be
generated after a successful write of a data byte into the
MAX1617.
Stop Condition (STOP)
Communications must be terminated by a stop condition
(a Low to High transition of SDA while SCL is High). The
Stop Condition must be communicated by the transmitter to
the MAX1617. (See SMBus Write/Read Timing Diagram.)
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