CM3202-02 Datasheet, PDF (8/11 Pages) ON Semiconductor – VTT Termination Voltage Regulator

CM3202−02
APPLICATION INFORMATION (Cont’d)
The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but
does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume
16.2 mA to achieve the 405 mV minimum over V_TT needed at the receiver:
I_terminaton
+
405 mV
Rt(25 W)
+
16.2 mA
A typical 64 Mbyte SSTL−2 memory system, with 128 terminated lines, has a worst−case maximum V_TT supply current up
to ±2.07 A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if
they ever occur at all. These high current peaks can be handled by the V_TT external capacitor. In a real memory system, the
continuous average V_TT current level in normal operation is less than ±200 mA.
The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers
and other circuitry. The current level typically stays within a range of 0.5 A to 1 A, with peaks up to 2 A or more, depending
on memory size and the computing operations being performed.
The tight tracking requirements and the need for V_TT to sink, as well as source, current provide unique challenges for
powering DDR SDRAM.
CM3202−02 Regulator
The CM3202−02 dual output linear regulator provides all of the power requirements of DDR memory by combining two
linear regulators into a single TDFN−8 package. VDDQ regulator can supply up to 2 A current, and the two−quadrant V_TT
termination regulator has current sink and source capability to ±2 A. The VDDQ linear regulator uses a PMOS pass element
for a very low dropout voltage, typically 500 mV at a 2 A output. The output voltage of V_DDQ can be set by an external voltage
divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any
change of the load, from high current to low current or inversely. The second output, V_TT, is regulated at V_DDQ/2 by an internal
resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The V_TT regulator
can source, as well as sink, up to 2 A current. The CM3202−02 is designed for optimal operation from a nominal 3.3 VDC bus,
but can work with VIN up to 5 V. When operating at higher VIN voltages, attention must be given to the increased package
power dissipation and proportionally increased heat generation. Limited by the package thermal resistance, the maximum
output current of the device at higher VIN cannot exceed the limit imposed by the maximum power dissipation value.
V_REF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate V_REF
can be created with a simple voltage divider of precision, matched resistors from V_DDQ to ground. A small ceramic bypass
capacitor can also be added for improved noise performance.
Input and Output Capacitors
The CM3202−02 requires that at least a 220 mF electrolytic capacitor be located near the VIN pin for stability and to maintain
the input bus voltage during load transients. An additional 4.7 mF ceramic capacitor between the VIN and GND, located as close
as possible to those pins, is recommended to ensure stability.
At a minimum, a 220 mF electrolytic capacitor is recommended for the V_DDQ output. An additional 4.7 mF ceramic capacitor
between the V_DDQ and GND, located very close to those pins, is recommended.
At a minimum, a 220 mF electrolytic capacitor is recommended for the V_TT output. This capacitor should have low ESR to
achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice.
In addition, place a 4.7 mF ceramic capacitor between the V_TT pin and GND, located very close to those pins. The total ESR
must be low enough to keep the transient within the V_TT window of 40 mV during the transition for source to sink. An average
current step of ±0.5 A requires:
ESR
t
40 mV
1 A
+
40 mW
Both outputs will remain stable and in regulation even during light or no load conditions.
The general recommendation for circuit stability for the CM3202−02 requires the following:
1. C_IN = C_DDQ = C_TT = 220 mF/4.7 mF for the full temperature range of –40 to +85°C.
2. C_IN = C_DDQ = C_TT = 100 mF/2.2 mF for the temperature range of –25 to +85°C.
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