CAT5241WI-25 Datasheet, PDF (8/16 Pages) ON Semiconductor – Quad Digitally Programmable Potentiometer with 64 Taps and I²C Interface

CAT5241
INSTRUCTIONS AND REGISTER
DESCRIPTION
SLAVE ADDRESS BYTE
The first byte sent to the CAT5241 from the
master/processor is called the Slave/DPP Address
Byte. The most significant four bits of the slave
address are a device type identifier. These bits for the
CAT5241 are fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the CAT5241 to successfully continue the com-
mand sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3 - A0 inputs
can be actively driven by CMOS input signals or tied
to V_CC or V_SS.
INSTRUCTION BYTE
The next byte sent to the CAT5241 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The P1 and P0 bits point to one of four
Wiper Control Registers. The least two significant bits,
R1 and R0, point to one of the four data registers of
each associated potentiometer. The format is shown
in Table 2.
Data Register Selection
Data Register Selected R1 R0
DR0
0
0
DR1
0
1
DR2
DR3
1
0
1
1
Table 1. Identification Byte Format
Device Type
Identifier
ID3
ID2
ID1
ID0
A3
0
1
0
1
(MSB)
Slave Address
A2
A1
A0
(LSB)
Table 2. Instruction Byte Format
I3
(MSB)
Instruction
Opcode
I2
I1
WCR/Pot Selection
Data Register
Selection
I0
P1
P0
R1
R0
(LSB)
Doc. No. MD-2011 Rev. Q
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice