AMIS39100PNPB3RG Datasheet, PDF (8/12 Pages) ON Semiconductor – Octal High Side Driver with Protection

AMIS−39100
Ground Loss
Due to its design, the AMIS−39100 is protected for
withstanding module ground loss and driver output shorted
to ground at the same time.
Table 10. POWER LOSS
VDDN
VB
Possible Case
0
0
System stopped
0
1
Start case or sleeping mode with missing V_DDN
1
0
Missing VB supply
VDDN normally present
1
1
System functional
Action
Nothing
Eight switches in the off−state
Power down consumption on VB
Eight switches in the off−state
Normal consumption on VDDN
Nominal functionality
SPI INTERFACE
The serial peripheral interface (SPI) is used to allow an
external microcontroller (MCU) to communicate with the
device. The AMIS−39100 acts always as a slave and it can’t
initiate any transmission.
SPI Transfer Format and Pin Signals
The SPI block diagram and timing characteristics are
shown in and Figures 5 and 6.
During an SPI transfer, data is simultaneously sent to and
received from the device. A serial clock line (CLK)
synchronizes shifting and sampling of the information on
the two serial data lines (DIN and DOUT). DOUT signal is
the output from the AMIS−39100 to the external MCU and
DIN signal is the input from the MCU to the AMIS−39100.
The WR−pin selects the AMIS−39100 for communication
and can also be used as a chip select (CS) in a multiple−slave
system. The WR−pin is active low. If AMIS−39100 is not
selected, DOUT is in high impedance state and it does not
interfere with SPI bus activities. Since AMIS−39100 always
shifts data out on the rising edge and samples the input data
also on the rising edge of the CLK signal, the MCU SPI port
must be configured to match this operation. SPI clock idles
high between the transferred bytes.
The diagram in Figure 6 represents the SPI timing
diagram for 8−bit communication.
Communication starts with a falling edge on the WR−pin
which latches the status of the diagnostic register into the
SPI output register. Subsequently, the CMD_x bits –
representing the newly requested driver status – are shifted
into the input register and simultaneously, the DIAG_x bits
– representing the actual output status – are shifted out. The
bits are shifted with x = 1 first and ending with x = 8.
At the rising edge of the WR−pin, the data in the input
register is latched into the command register and all drivers
are simultaneously switching to the newly requested status.
SPI communication is ended.
In case the SPI master does only support 16−bit
communication, then the master must first send 8 clock
pulses with dummy DIN data and ignoring the DOUT data.
For the next 8 clock pulses the above description can be
applied.
The required timing for serial to peripheral interface is
shown in Table 11.
Table 11. DIGITAL CHARACTERISTICS
Symbol
T_CLK
T_DATA_ready
Description
Maximum applied clock frequency on CLK input
Time between falling edge on WR and first bit of data ready on DOUT
output (driver going from HZ state to output of first diagnostic bit)
Min
Max
Unit
500
kHz
2
ms
T_CLK_first
T_setup (Note 13)
T_hold (Note 13)
T_DATA_next
First clock edge from falling edge on WR
Setup time on DIN
Hold time on DIN
Time between rising edge on CLK and next bit ready on DOUT (capa on
DOUT is 30 pF max.)
3
ms
20
ns
20
ns
100
ns
T_SPI_END
T_risefall
Time between last CLK edge and WR rising edge
1
ms
Rise and fall time of all applied signals (maximum loading capacitance is
5
20
ns
30 pF)
T_WR
Time between two rising edge on WR (repetition of the same command)
300
ms
13. Guaranteed by design.
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