NV25M01 Datasheet, PDF (7/13 Pages) ON Semiconductor – 1 Mb SPI Serial CMOS EEPROM

NV25M01
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 24−bit address
and a data byte as shown in Figure 5. Only 17 significant
address bits are used by the NV25M01. The rest are don’t
care bits, as shown in Table 11. Internal programming will
start after the low to high CS transition. During an internal
write cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The RDY bit will indicate if the
internal write cycle is in progress (RDY high), or the device
is ready to accept commands (RDY low).
Page Write
After sending the first data byte to the NV25M01, the host
may continue sending data, up to a total of 256 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previoualy loaded data.
Following completion of the write cycle, the NV25M01 is
automatically returned to the write disable state.
Write Identification Page
The 256−byte Identification Page (IP) can be written with
user data using the same Write commands sequences that are
used for writing to the main memory array (Figure 6). The
IPL Status Register bit must be set (IPL = 1), before
attempting to write to the IP.
Address bits [A23:A17] and [A14:A8] are Don’t Care and
address bits [A7:A0] determine the starting byte address
within the Identification Page. Address bits [A16:A15] must
point to a location outside the protected area defined by
Write Protection bits BP1 and BP0. When the entire memory
is write protected (BP1, BP0 = 1,1), write requests to the IP
will be ignored.
A write request to the IP is also ignored if the LIP Status
Register bit is set to 1 (the page is locked in Read−only
mode).
Table 11. BYTE ADDRESS
Device
Address Significant Bits
Main Memory Array
A16 − A0
Identification Page
(A16:15) and A7 − A0
Address Don’t Care Bits
A23 – A17
A23 – A17 & A14 − A8
# Address Clock Pulses
24
24
CS
SCK
SI
012345678
29 30 31 32 33 34 35 36 37 38 39
OPCODE
BYTE ADDRESS*
DATA IN
0 0 0 0 0 0 1 0 ^AN
A_{0 D7 D6 D5 D4 D3 D2 D1 D0}
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 11)
Note: Dashed Line = mode (1, 1)
Figure 5. Byte WRITE Timing
CS
SCK
SI
012345678
29 30 31 32−39 40−47 32+(N−1)x8−1....32+(N−1)x8
32+Nx8−1
OPCODE
00 00 00
BYTE ADDRESS*
DATA IN
1 0 A_N
A₀
Data Data
Byte 1 Byte 2
Data Byte N
7..1 0
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 11)
Note: Dashed Line = mode (1, 1)
Figure 6. Page WRITE Timing
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