NLSX3018_13 Datasheet, PDF (7/12 Pages) ON Semiconductor – 8-Bit 100 Mb/s Configurable Dual-Supply Level Translator

NLSX3018
ENABLE / DISABLE TIME MEASUREMENTS
−405C to +855C
Symbol
Parameter
Test Conditions
(Note 12)
V_CC (V)
(Note 13)
V_L (V)
(Note 14)
Typ
Min (Note 15) Max Unit
t_EN−VCC Turn−On Enable Time (Output =
I/O_V_CC, t_pZH)
C_IOVCC = 15 pF 1.3 to 4.5 0.9 to (V_CC – 0.4)
130
180 ns
t_EN−VL
Turn−On Enable Time (Output =
I/O_V_CC, t_pZL)
Turn−On Enable Time (Output =
I/O_V_L, t_pZH)
Turn−On Enable Time (Output =
I/O_V_L, t_pZL)
C_IOVL = 15 pF
C_IOVCC = 15 pF
C_IOVL = 15 pF
1.3 to 4.5 0.9 to (V_CC – 0.4)
1.3 to 4.5 0.9 to (V_CC – 0.4)
1.3 to 4.5 0.9 to (V_CC – 0.4)
100
150 ns
95
185 ns
70
110 ns
t_DIS−VCC Turn−Off Disable Time (Output =
I/O_V_CC, t_pHZ)
C_IOVCC = 15 pF 1.3 to 4.5 0.9 to (V_CC – 0.4)
175
250 ns
Propagation Delay (Output =
I/O_V_CC, t_PLZ)
C_IOVL = 15 pF
1.3 to 4.5 0.9 to (V_CC – 0.4)
150
190 ns
t_DIS−VL Turn−Off Disable Time (Output =
I/O_V_L, t_pHZ)
C_IOVCC = 15 pF 1.3 to 4.5 0.9 to (V_CC – 0.4)
180
250 ns
Propagation Delay (Output = I/O_V_L,
t_PLZ)
C_IOVL = 15 pF
1.3 to 4.5 0.9 to (V_CC – 0.4)
160
220 ns
12. Normal test conditions are V_EN = 0 V, C_IOVCC = 15 pF and C_IOVL = 15 pF, unless otherwise specified.
13. V_CC is the supply voltage associated with the high voltage port, and V_CC ranges from +1.3 V to 4.5 V under normal operating conditions.
14. V_L is the supply voltage associated with the low voltage port. V_L must be less than or equal to (V_CC – 0.4) V during normal operation. However,
during startup and shutdown conditions, V_L can be greater than (V_CC – 0.4) V.
15. Typical values are for V_CC = +2.8 V, V_L = +1.8 V and T_A = +25 °C. All units are production tested at T_A = +25 °C. Limits over the operating
temperature range are guaranteed by design.
V_L
Source
NLSX3018
EN
I/O V_L
V_CC
I/O V_CC
C_IOVCC
I/O V_L
90%
50%
10%
I/O V_CC^{tPD_VL−VCC}
90%
50%
10%
t_RISE/FALL v
3 ns
t_F−VCC
t_{PD_VL−VCC}
t_R−VCC
Figure 4. Driving I/O V_L Test Circuit and Timing
V_L
I/O V_L
C_IOVL
NLSX3018
EN
I/O V_CC
90%
50%
10%
I/O V_L^{tPD_VCC−VL}
90%
50%
10%
t_RISE/FALL v 3 ns
t_F−VL
V_CC
I/O V_CC
Source
t_{PD_VCC−VL}
t_R−VL
Figure 5. Driving I/O V_CC Test Circuit and Timing
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