MC44608_06 Datasheet, PDF (7/15 Pages) ON Semiconductor – Few External Components Reliable and Flexible SMPS Controller

MC44608
OSC
4V
Vcont
2.4 V
Clock
V _CC
13 V
10 V
6.5 V
DMG
Iprim
Figure 6.
The OSC and Clock signals are provided according to the
Figure 6. The Clock signals correspond to the CT capacitor
discharge. The bottom curve represents the current flowing
in the sense resistor Rcs. It starts from zero and stops when
the sawtooth value is equal to the control voltage Vcont. In
this way the SMPS is regulated with a voltage mode control.
Overvoltage Protection
The MC44608 offers two OVP functions:
− a fixed function that detects when V_CC is higher than
15.4 V
− a programmable function that uses the demag pin. The
current flowing into the demag pin is mirrored and
compared to the reference current Iovp (120 mA). Thus this
OVP is quicker as it is not impacted by the V_CC inertia and
is called QOVP.
In both cases, once an OVP condition is detected, the
output is latched off until a new circuit startup.
Startup Management
The V_i pin 8 is directly connected to the HV DC rail Vin.
This high voltage current source is internally connected to
the V_CC pin and thus is used to charge the V_CC capacitor. The
V_CC capacitor charge period corresponds to the startup
phase. When the V_CC voltage reaches 13 V, the high voltage
9.0 mA current source is disabled and the device starts
working. The device enters into the switching phase.
It is to be noticed that the maximum rating of the V_i pin 8
is 500 V. ESD protection circuitry is not currently added to
this pin due to size limitations and technology constraints.
Protection is limited by the drain−substrate junction in
avalanche breakdown. To help increase the application
safety against high voltage spike on that pin it is possible to
insert a small wattage 1.0 kW series resistor between the V_in
rail and pin 8.
The Figure 7 shows the V_CC voltage evolution in case of
no external current source providing current into the V_CC
pin during the switching phase. This case can be
encountered in SMPS when the self supply through an
auxiliary winding is not present (strong overload on the
SMPS output for example). The Figure 17 also depicts this
working configuration.
Startup
Phase
Latched off
Phase
Figure 7. Hiccup Mode
Switching
Phase
In case of the hiccup mode, the duty cycle of the switching
phase is in the range of 10%.
Mode Transition
The LW latch Figure 8 is the memory of the working status
at the end of every switching sequence.
Two different cases must be considered for the logic at the
termination of the SWITCHING PHASE:
1. No Over Current was observed
2. An Over Current was observed
These 2 cases are corresponding to the signal labelled
NOC in case of “No Over Current” and “OC” in case of Over
Current. So the effective working status at the end of the ON
time memorized in LW corresponds to Q=1 for no over
current and Q=0 for over current.
This sequence is repeated during the Switching phase.
Several events can occur:
1. SMPS switch OFF
2. SMPS output overload
3. Transition from Normal to Pulsed Mode
4. Transition from Pulsed Mode to Normal Mode
Latched Off
Phase
VPWM
OUT
LEB out
1V
& ^NOC S Q
OC ^LW
&
SQ
Mode
Standby
&
R Q & R1
R2
+
CS
−
Startup Idemag Switching Startup
Phase > 24 mA Phase Phase
S1
Switch
Figure 8. Transition Logic
• 1. SMPS SWITCH OFF
When the mains is switched OFF, so long as the bulk
electrolithic bulk capacitor provides energy to the SMPS,
the controller remains in the switching phase. Then the peak
current reaches its maximum peak value, the switching
frequency decreases and all the secondary voltages are
reduced. The V_CC voltage is also reduced. When V_CC is
equal to 10 V, the SMPS stops working.
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