MC34261 Datasheet, PDF (7/13 Pages) Motorola, Inc – POWER FACTOR CONTROLLERS

MC34261, MC33261
With the component values shown in Figure 16, the
Current Sense Comparator threshold, at the peak of the
haversine varies from 1.1 V at 90 Vac to 100 mV at 268 Vac.
The Current Sense Input to Drive Output propagation delay
is typically 200 ns.
wide input range off line preconverter applications. An
internal 36 V clamp has been added from V_CC to ground to
protect the IC and capacitor C₅ from an overvoltage
condition. This feature is desirable if external circuitry is
used to delay the startup of the preconverter.
Timer
A watchdog timer function was added to the IC to
eliminate the need for an external oscillator when used in
stand alone applications. The Timer provides a means to
automatically start or restart the preconverter if the Drive
Output has been off for more than 400 μs after the inductor
current reaches zero.
Undervoltage Lockout
An Undervoltage Lockout comparator guarantees that the
IC is fully functional before enabling the output stage. The
positive power supply terminal (V_CC) is monitored by the
UVLO comparator with the upper threshold set at 10 V and
the lower threshold at 8.0 V (Figure 14). In the standby
mode, with V_CC at 7.0 V, the required supply current is less
than 0.5 mA (Figure 13). This hysteresis and low startup
current allow the implementation of efficient bootstrap
startup techniques, making these devices ideally suited for
Output
The MC34261/MC33261 contain a single totem pole
output stage specifically designed for direct drive of power
MOSFETs. The Drive Output is capable of up to ±500 mA
peak current with a typical rise and fall time of 50 ns with a
1.0 nF load. Additional internal circuitry has been added to
keep the Drive Output in a sinking mode whenever the
Undervoltage Lockout is active. This characteristic
eliminates the need for an external gate pull−down resistor.
The totem pole output has been optimized to minimize cross
conduction current during high speed operation. The
addition of two 10 Ω resistors, one in series with the source
output transistor and one in series with the sink output
transistor, reduces the cross conduction current, as shown in
Figure 12. A 16 V clamp has been incorporated into the
output stage to limit the high state V_OH. This prevents
rupture of the MOSFET gate when V_CC exceeds 20 V.
Table 1. Design Equations
Notes
Calculation
Formula
Calculate the maximum required output power.
Calculated at the minimum required ac line for regula-
tion. Let the efficiency n = 0.95.
Let the switching cycle t = 20 μs.
Required Converter Output Power
Peak Inductor Current
Inductance
In theory the on−time t_on is constant. In practice t_on
tends to increase at the ac line zero crossings due to
the charge on capacitor C₆.
The off−time t_off is greatest at peak ac line
and approaches zero at the ac line zero
crossings. Theta (θ) represents the angle of
the ac line voltage.
The minimum switching frequency occurs at peak ac
line and increases as t_off decreases.
Set the current sense threshold V_CS to 1.0 V for
universal input (85 Vac to 265 Vac) operation
and to 0.5 V for fixed input (92 Vac to 138 Vac,
or 184 to 276 Vac) operation.
Set the multiplier input voltage V_M to 3.0 V at high
line. Empirically adjust V_M for the lowest distortion
over the ac line range while guaranteeing startup
at minimum line.
The I_IB R₁ error term can be minimized with a divider
current in excess of 100 μA.
Switch On−Time
Switch Off−Time
Switching Frequency
Peak Switch Current
Multiplier Input Voltage
Converter Output Voltage
The bandwidth is typically set to 20 Hz for minimum
output ripple over the ac line haversine.
Error Amplifier Bandwidth
The following converter characteristics must be chosen:
V_O − Desired output voltage
I_O − Desired output current
Vac − AC RMS line voltage
Vac_(LL) − AC RMS low line voltage
P_O = V_O I_O
I_L(pk) =
2 2 P_O
ηVac_(LL)
ǒ Ǔ 2t VO − Vac Vac2
2
L=
V_O Vac_(LL) I_L(pk)
t_on =
2 P_O L
η Vac²
t_off =
t_on
V_O
−1
2 Vac ⎪Sin θ⎜
f= ¹
t_on + t_off
R₉ =
V_CS
I_L(pk)
ǒ Ǔ ^{VM =}
Vac 2
R_{7 + 1}
R₃
ǒ Ǔ _{VO = Vref}
R_{2 + 1}
R₁
− I_IB R₂
BW =
1
R₁ R₂
2 π _{R1 + R2} C₁
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