CS4124 Datasheet, PDF (7/12 Pages) Cherry Semiconductor Corporation – High Side PWM FET Controller

CS4124
APPLICATIONS INFORMATION
THEORY OF OPERATION
Oscillator
The IC sets up a constant frequency triangle wave at the
C_OSC lead whose frequency is related to the external
components R_OSC and C_OSC, by the following equation:
Frequency
+
0.83
ROSC COSC
The peak and valley of the triangle wave are proportional
to V_CC by the following:
VVALLEY + 0.1 VCC
VPEAK + 0.7 VCC
This is required to make the voltage compensation
function properly. In order to keep the frequency of the
oscillator constant the current that charges C_OSC must also
vary with supply. R_OSC sets up the current which charges
C_OSC. The voltage across R_OSC is 50% of V_CC and
therefore:
IROSC + 0.5
VCC
ROSC
I_ROSC is multiplied by (2) internally and transferred to the
C_OSC lead. Therefore:
ICOSC
+"
VCC
ROSC
The period of the oscillator is:
T + 2COSC
VPEAK * VVALLEY
ICOSC
The R_OSC and C_OSC components can be varied to create
frequencies over the range of 15 Hz to 25 kHz. With the
suggested values of 93.1 kΩ and 470 pF for R_OSC and C_OSC,
the nominal frequency will be approximately 20 kHz.
I_ROSC, at V_CC = 14 V, will be 66.7 µA. I_ROSC should not
change over a more than 2:1 ratio and therefore C_OSC should
be changed to adjust the oscillator frequency.
Voltage Duty Cycle Conversion
The IC translates an input voltage at the CTL lead into a
duty cycle at the OUTPUT lead. The transfer function
incorporates ON Semiconductor’s patented Voltage
Compensation method to keep the average voltage and
current across the load constant regardless of fluctuations in
the supply voltage. The duty cycle is varied based upon the
input voltage and supply voltage by the following equation:
Duty Cycle + 100%
2.8 VCTL
VCC
An internal DC voltage equal to:
VDC + (1.683 VCTL) ) VVALLEY
is compared to the oscillator voltage to produce the
compensated duty cycle. The transfer is set up so that when
V_CC = 14 V the duty cycle will equal V_CTL divided by V_REG.
For example at V_CC = 14 V, V_REG = 5.0 V and V_CTL = 2.5 V,
the duty cycle would be 50% at the output. This would place
a 7.0 V average voltage across the load. If V_CC then drops
to 10 V, the IC would change the duty cycle to 70% and
hence keep the average load voltage at 7.0 V.
120
100
V_CC = 8.0 V
80
V_CC = 14 V
60
40
V_CC = 16 V
20
0
10 20 30 40 50 60 70 80 90 100
CTL Voltage (% of V_REG)
Figure 7. Voltage Compensation
5.0 V Linear Regulator
There is a 5.0 V, 5.0 mA linear regulator available at the
V_REG lead for external use. This voltage acts as a reference
for many internal and external functions. It has a drop out of
approximately 1.5 V at room temperature.
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the I_SENSE+ and I_SENSE– leads. The
differential voltage across these two leads is amplified
internally and compared to the voltage at the I_ADJ lead. The
gain, A_V is set internally and externally by the following
equation:
AV
+
VI(ADJ)
ISENSE₎ * ISENSE_*
+
37000
1000 ) RCS
The current limit (I_LIM) is set by the external current sense
resistor (R_SENSE) placed across the I_SENSE+ and I_SENSE–
terminals and the voltage at the I_ADJ lead.
ILIM
+
1000 ) RCS
37000
VI(ADJ)
RSENSE
The R_CS resistors and C_CS components form a differential
low pass filter which filters out high frequency noise
generated by the switching of the external MOSFET and the
associated lead noise. R_CS also forms an error term in the
gain of the I_LIM equation because the I_SENSE+ and I_SENSE–
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50 µA while the
chip is in run mode. I_ADJ should be biased between 1.0 V and
4.0 V. When the current through the external MOSFET
exceeds I_LIM, an internal latch is set and the output pulls the
gate of the MOSFET low for the remainder of the oscillator
cycle (fault mode). At the start of the next cycle, the latch is
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