CM3202-02DE Datasheet, PDF (7/11 Pages) ON Semiconductor – DDR VDDQ and VTT Termination Voltage Regulator

CM3202−02
TYPICAL OPERATING CHARACTERISTICS (Cont’d)
VDDQ Transient Response
I_DDQ
0.5A/div
V_IN = 3.3V
V_DDQ
0.1V/div
VTT Transient Response
V_IN
I_TT
0.5A/div
-0.75A
VTT
0.1V/div
TIME (0.2ms/div)
TIME (0.2ms/div)
APPLICATION INFORMATION
Powering DDR Memory
Double−Data−Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic
systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle
versus one. DDR SDRAMs transmit data at both the rising and falling edges of the memory bus clock.
DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power−supply rejection, while
reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management
architecture than previous RAM technology.
Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface
signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by
lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use
of a termination voltage, V_TT. SSTL_2 is an industry standard defined in JEDEC document JESD8−9. SSTL_2 maintains
high−speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM
specification in JESD79C.
DDR memory requires three tightly regulated voltages: V_DDQ, V_TT, and V_REF (see Typical DDR terminations, Class II). In
a typical SSTL_2 receiver, the higher current V_DDQ supply voltage is normally 2.5 V with a tolerance of ±200 mV. The active
bus termination voltage, V_TT, is half of V_DDQ. V_REF is a reference voltage that tracks half of V_DDQ ±1%, and is compared with
the V_TT terminated signal at the receiver. V_TT must be within ±40 mV of V_REF
VDDQ
VTT (=VDDQ/2) VDDQ
Rs = 25
Transmitter
Rt = 25
Line
+
−
Receiver
VREF (=VDDQ/2)
Figure 1. Typical DDR Terminations, Class II
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