CAV25080YE-GT3 Datasheet, PDF (7/13 Pages) ON Semiconductor – 8-Kb and 16-Kb SPI Serial CMOS EEPROM

CAV25080, CAV25160
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 10 significant address
bits are used by the CAV25080 and 11 by the CAV25160.
The rest are don’t care bits, as shown in Table 11. Internal
programming will start after the low to high CS transition.
During an internal write cycle, all commands, except for
RDSR (Read Status Register) will be ignored. The RDY bit
will indicate if the internal write cycle is in progress (RDY
high), or the device is ready to accept commands (RDY
low).
Table 11. BYTE ADDRESS
Device
CAV25080
CAV25160
Address Significant Bits
A9 − A0
A10 − A0
Page Write
After sending the first data byte to the CAV25080/160, the
host may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the
CAV25080/160 is automatically returned to the write
disable state.
Address Don’t Care Bits
A15 − A10
A15 − A11
# Address Clock Pulse
16
16
CS
SCK
SI
012345678
21 22 23 24 25 26 27 28 29 30 31
00
OPCODE
00 0 01
BYTE ADDRESS*
DATA IN
0 A_N
A₀ D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 5. Byte WRITE Timing
CS
SCK
012345678
21 22 23 24−31 32−39 ^{24+(N−1)x8−1 .. 24+(N−1)x8}
24+Nx8−1
OPCODE
BYTE ADDRESS*
DATA IN
Data Byte N
SI
0 0 0 0 0 0 1 0 AN
A₀
7..1 0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
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