CAT25010 Datasheet, PDF (7/15 Pages) Catalyst Semiconductor – 1K/2K/4K SPI Serial CMOS EEPROM

CAT25010, CAT25020, CAT25040
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2 and 3 can be written using the WRSR command.
Write Protection
When WP input is low all write operations to the memory
array and Status Register are inhibited. WP going low while
CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going
low will have no effect on any write operation to the Status
Register. The WP input timing is shown in Figure 8.
CS
SCK
0
1
2
3
45
6
7
8
9 10 11 12 13 14 15
OPCODE
SI
0
0
0
0
00
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
0
1
7
6
5
MSB
Figure 7. WRSR Timing
DATA IN
4 32
10
t_WPS
t_WPH
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
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