CAT1025JI-30 Datasheet, PDF (7/20 Pages) ON Semiconductor – Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset

CAT1024, CAT1025
DEVICE OPERATION
Reset Controller Description
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
During power-up, the RESET outputs remain active
until V_CC reaches the V_TH threshold and will continue
driving the outputs for approximately 200 ms (t_PURST)
after reaching V_TH. After the t_PURST timeout interval, the
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
During power-down, the RESET outputs will be active
when V_CC falls below V_TH. The R¯¯E¯S¯E¯T¯ output will be
valid so long as V_CC is >1.0 V (V_RVALID). The device is
designed to ignore the fast negative going V_CC transi-
ent pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
The R¯¯E¯S¯E¯T¯ pin can operate as reset output and
manual reset input. The input is edge triggered; that
is, the R¯¯E¯S¯E¯T¯ input will initiate a reset timeout after
detecting a high to low transition.
When R¯¯E¯S¯E¯T¯ I/O is driven to the active state, the
200 ms timer will begin to time the reset interval. If
external reset is shorter than 200 ms, Reset outputs
will remain active at least 200 ms.
The CAT1024/25 also have a separate manual reset
input. Driving the ^{¯M¯R¯} input low by connecting a
pushbutton (normally open) from ^{¯M¯R¯} pin to GND will
generate a reset condition. The input has an internal
pull up resistor.
Reset remains asserted while ^{¯M¯R¯} is low and for the
Reset Timeout period after ^{¯M¯R¯} input has gone high.
Glitches shorter than 100 ns on ^{¯M¯R¯} input will not ge-
nerate a reset pulse. No external debouncing circuits
are required. Manual reset operation using ^{¯M¯R¯} input
is shown in Figure 2.
Hardware Data Protection
The CAT1024/25 supervisors have been designed to
solve many of the data corruption issues that have long
been associated with serial EEPROMs. Data corruption
occurs when incorrect data is stored in a memory
location which is assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal non-
volatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5 ms) before V_CC reaches the minimum value of 2 V.
In addition, the CAT1025 includes a Write Protection
Input which when tied to V_CC will disable any write
operations to the device.
© 2009 SCILLC. All rights reserved.
7
Characteristics subject to change without notice
Doc. No. MD-3008 Rev. R