74HC595 Datasheet, PDF (7/13 Pages) NXP Semiconductors – 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

74HC595
FUNCTION TABLE
Operation
Reset shift register
Reset
L
Serial
Input
A
X
Inputs
Shift
Clock
X
Latch
Clock
L, H, ↓
Output
Enable
L
Shift
Register
Contents
L
Resulting Function
Latch
Register
Contents
Serial
Output
SQ_H
U
L
Parallel
Outputs
Q_A − Q_H
U
Shift data into shift
register
H
D
↑
L, H, ↓
L
D→SR_A;
U
SR_G→SR_H
U
SR_N→SR_N+1
Shift register remains
H
X
L, H, ↓ L, H, ↓
L
U
unchanged
U
U
U
Transfer shift register
H
X
L, H, ↓
↑
L
contents to latch
register
U
SR_N→LR_N
U
SR_N
Latch register remains
X
X
X
L, H, ↓
L
*
unchanged
U
*
U
Enable parallel outputs
X
X
X
X
L
*
**
*
Enabled
Force outputs into high
X
X
X
X
H
*
impedance state
**
*
Z
SR = shift register contents
LR = latch register contents
D = data (L, H) logic level
U = remains unchanged
↑ = Low−to−High
↓ = High−to−Low
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8−bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low− to−high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
Reset (Pin 10)
Active−low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low−to−high transition on
this input latches the shift register data.
Output Enable (Pin 13)
Active−low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (Q_A−Q_H) into the
high−impedance state. The serial output is not affected by
this control unit.
OUTPUTS
Q_A − Q_H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3−state, latch outputs.
SQ_H (Pin 9)
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
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