PACVGA105 Datasheet, PDF (6/9 Pages) California Micro Devices Corp – VGA Port Companion Circuit

PACVGA105
ELECTRICAL OPERATING CHARACTERISTICS ^{(SEE NOTE 1)}
SYMBOL PARAMETER
V
Diode Forward Voltage
F
V
Logic High Output Voltage
OH
V_OL
Logic Low Output Voltage
I
Input Current
IN
R, G and B pins
HSYNC, VSYNC pins
HSYNC, VSYNC pins
I_CC
V_CC Supply Current
CONDITIONS
I = 10mA
F
I = -4mA, V = 4.5V
OH
CC
I_OL = 4mA, V_CC = 4.5V
MIN TYP MAX UNITS
1.0
V
4.0
V
0.4
V
V_RGB = 3.63V, V_IN = V_RGB or GND
V = 3.63V, V = V
AUX
IN
AUX
V = 3.63V, V = GND
AUX
IN
+1
μA
+1
μA
-30 -72.5 -95 μA
V_CC = 5.5V; V_AUX = V_RGB = 2.97V; All inputs
and outputs floating
35 100 μA
I_RGB
V_RGB Supply Current
R, G and B pins at V_CC or GND; All
inputs and outputs floating
10
μA
C
Input Capacitance
IN
R, G and B pins
Note 2 applies for all cases
HSYNC, VSYNC pins
DDC_DATA, DDC_CLK pins
5
pF
10
pF
5
pF
R
Pull-up Resistance
PU
DDC_DATA, DDC_CLK pins
1.62 1.8 1.98 kΩ
V
ESD Withstand Voltage
ESD
V = 5V; V = 3.3V;
CC
RGB
±8
kV
V_AUX = 3.3V; Note 3
t
SYNC Buffer L => H
PLH
Propagation Delay
C = 50pF; V = 5.0V;
L
CC
R = 500Ω; Note 4
L
7.0 15.0 ns
t_PHL
SYNC Buffer H => L
Propagation Delay
C_L = 50pF; V_CC = 5.0V;
R_L = 500Ω; Note 4
7.0 15.0 ns
tt
SYNC Buffer Output Rise & Fall C = 50pF; V = 5.0V;
R, F
L
CC
Times
R = 500Ω; Note 4
L
7.0
ns
Note 1: All parameters specified over standard operating conditions unless otherwise noted.
Note 2: Measured at 1MHz. R/G/B inputs biased at 1.65V with V_RGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V with
V_CC=5V. HSYNC and VSYNC inputs biased at V_AUX or GND with V_AUX = 3.3V and V_CC = 5V.
Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V_RGB and V_CC must be bypassed
to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin.
ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to
GND. Applicable pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC
inputs are ESD protected to the industry standard 2kV per the Human Body Model (MIL-STD-883, Method 3015).
Note 4: Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times ≤ 5ns.
Guaranteed by correlation to buffer output drive currents.
Rev. 2 | Page 6 of 9 | www.onsemi.com