PACDN004 Datasheet, PDF (6/9 Pages) California Micro Devices Corp – 2 CHANNEL ESD PROTECTION ARRAY

PACDN004
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the ESD protection device. Refer to Application of
Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD
pulse striking an input channel. The parasitic series inductance back to the power supply is represented
by L₁ and L₂. The voltage V_CL on the line being protected is:
V_CL = Fwd voltage drop of D₁ + V_SUPPLY + L₁ x d(I_ESD ) / dt+ L₂ x d(I_ESD ) / dt
where I_ESD is the ESD current pulse, and V_SUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I_ESD)/dt can be approximated by ΔI_ESD/Δt, or 30/(1x10^-9). So just 10nH of series
inductance (L₁ and L₂ combined) will lead to a 300V increment in V_CL!
Similarly for negative ESD pulses, parasitic series inductance from the V_N pin to the ground rail will lead to
drastically increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to fast transient current spikes. In the V_CL equation
above, the V_SUPPLY term, in reality, is given by (V_DC + I_ESD x R_OUT), where V_DC and R_OUT are the nominal supply
DC output voltage and effective output impedance of the power supply respectively. As an example, a
R_OUT of 1 ohm would result in a 10V increment in V_CL for a peak I_ESD of 10A.
If the inductances and resistance described above are close to zero, the rail-clamp ESD protection diodes
will do a good job of protection. However, since this is not possible in practical situations, a bypass
capacitor must be used to absorb the very high frequency ESD energy. So for any brand of rail-clamp
ESD protection diodes, a bypass capacitor should be connected between the V_P pin of the diodes and the
ground plane (V_N pin of the diodes) as shown in the Application Circuit diagram below. A value of 0.22µF
is adequate for IEC-61000-4-2 level 4 contact discharge protection (+8kV). Ceramic chip capacitors
mounted with short printed circuit board traces are good choices for this application. Electrolytic
capacitors should be avoided as they have poor high frequency characteristics. For extra protection,
connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series
inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher
than the maximum supply voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of
expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as
close to the V_P pin of the Protection Array as possible, with minimum PCB trace lengths to the power
supply, ground planes and between the signal input and the ESD device to minimize stray series
inductance.
Additional Information
See also California Micro Devices Application Notes AP209, “Design Considerations for ESD Protection”
and AP219, "ESD Protection for USB 2.0 Systems"
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