NCP1588 Datasheet, PDF (6/10 Pages) ON Semiconductor – Low Voltage Synchronous Buck Controller

NCP1588
APPLICATIONS INFORMATION
Overcurrent Protection (OCP)
The low-side R_DSon sense is implemented by comparing
the voltage at the LX, at the end of LG on time to an
internally generated fixed voltage. If the phase voltage is
lower than OCP trip voltage, an overcurrent condition
occurs and a counter is initiated.
When the counter completes after two clock cycles, the
PWM logic and both HS-FET and LS-FET are turned off.
Power has to be recycled to exit out of the overcurrent fault.
The minimum turn-on time of the LS-FET is set to be
500 ns.
NCP1588 allows to easily program an Overcurrent
Threshold ranging from 50 mV to 550 mV, simply by
adding a resistor (ROCSET) between LG and GND. During
a short period of time following V_CC rising over UVLO
threshold, an internal 10 mA current (IOCSET) is sourced
from LG pin, determining a voltage drop across ROCSET.
This voltage drop will be sampled and internally held by the
device as OverCurrent Threshold. The OC setting procedure
overall time length is about 4.2 ms. Connecting a ROCSET
resistor between LG and GND, the programmed threshold
will be:
I_OCth
+
I_OCSET @ R_OCSET
R_DS(on)
RSET values range from 5 kW to 55 kW. In case ROCSET
is not connected, the device switches the OCP threshold to
a fixed 640 mV value: an internal safety clamp on BG is
triggered as soon as LG voltage reaches 700 mV, enabling
the 640 mV fixed threshold and ending OC setting phase.
The current trip threshold tolerance is ±25 mV. The accuracy
of the set point is best at the highest set point. The accuracy
will decrease as the set point decreases.
Internal Soft –Start
The NCP1588 features an internal soft-start function,
which reduces the inrush current and overshoot of the output
voltage. Figure 7. shows a typical soft-start sequence.
Soft-Start is achieved by ramping the internal reference
using the oscillator clock (64 steps from 0 V to 0.8 V of
V_REF). The order of startup sequence is as follows: UVLO
→ OCP programming → Comp voltage reach the lower end
of the Ramp voltage (1.1 V). The typical soft-start time is
4.2 ms. The internal soft-start is held low when the part is
in UVLO or Disable mode.
Power Good
Power Good is an open drain and active high output. This
output can be pulled up high to the appropriate level with an
external resistor. It monitors the output voltage through the
VOS pin. The PGOOD is flagged low for ±10% of Vout for
OV/UV trip points respectively. The separate VOS input is
not slowed down by the compensation on the VFB pin. The
PGOOD output can deliver a max of 4 mA sink current at
0.4 V when de-asserted. The PGOOD pin is held low during
soft-start. Once soft-start is complete PGOOD goes high if
there are no faults without any delays associated to it.
Undervoltage Protection
If the voltage at VOS pin drops below UV threshold, the
device turns off both HS and LS MOSFETs, latching the
condition. This requires a POR to recover.
Overvoltage Protection
If the voltage at VOS pin rises over OV threshold (1V typ),
overvoltage protection turns off UG MOSFET and turns on
LG MOSFET. The LG MOSFET will be turned off as soon
as VOS goes below Vref/2 (0.4 V). The condition is latched,
and requires POR to recover. The device still controls the LG
MOSFET and can switch it on whenever VOS rises above
0.4 V.
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