MC10E167_06 Datasheet, PDF (6/8 Pages) ON Semiconductor – 5V ECL 6-Bit 2:1 MUX-Register

MC10E167, MC100E167
Q
Driver
Device
Q
Z_o = 50 W
Z_o = 50 W
50 W
50 W
D
Receiver
Device
D
V_TT
V_TT = V_CC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
Shipping^†
MC10E167FN
PLCC−28
37 Units / Rail
MC10E167FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E167FNR2
PLCC−28
500 / Tape & Reel
MC10E167FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E167FN
PLCC−28
37 Units / Rail
MC100E167FNR2
PLCC−28
500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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