ENA2199 Datasheet, PDF (6/22 Pages) ON Semiconductor – 8M-bit (1024K x 8) Serial Flash Memory

LE25U81AQE
2. Dual read
There are two Dual read commands, the Dual Output read command and the Dual I/O read command. They achieve the
twice speed-up from a High-speed read command.
2-1. Dual Output read command
The Dual Output read command changes SI/SIO0 into the output pin function in addition to SO/SIO1, makes the data
output x2 bit and has achieved a high-speed output. Consisting of the first through fifth bus cycles, the Dual Output read
command inputs the 24-bit addresses and 8 dummy bits following (3Bh). DATA1 (Bit7, BIt5, Bit3 and Bit1) is output
from SI/SIO0 and DATA0 (Bit6, Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of fifth bus
cycle bit 0 as a reference. "Figure 5-a Dual Output read" shows the timing waveforms.
Figure 5-a Dual Output read
CS
SCK
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 43 44 47
SI/SIO0
SO/SIO1
MSB
8CLK
3Bh
2-2. Dual I/O read command
Add. Add.
High Impedance
Add.
dummy N
N+1 N+2
bit
DATA0 DATA0 DATA0 ^DATA0
b6,b4,b2,b0
4CLK 4CLK
DATA1 DATA1 DATA1 ^DATA1
b7,b5,b3,b1
MSB MSB MSB
The Dual I/O read command changes SI/SIO0 and SO/SIO1 into the input output pin function, makes the data input and
output x2 bit and has achieved a high-speed output. Consisting of the first through third bus cycles, the Dual I/O read
command inputs the 24-bit addresses and 4 dummy clocks following (BBh). The format of the address input and the
dummy bit input is the x2 bit input. Add1 (A23, A21, -, A3 and A1) is input from S0/SIO1 and Add0 (A22, A20, -, A2
and A0) is input from SI/SIO0. 2CLK of the latter half of the dummy clock is in the state of high impedance, the
controller can switch I/O for this period. DATA1 (Bit7, BIt5, Bit3 and Bit1) is output from SI/SIO0 and DATA0 (Bit6,
Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of third bus cycle bit 0 as a reference. "Figure 5-b
Dual I/O Read" shows the timing waveforms.
Figure 5-b Dual I/O Read
CS
SCK
SI/SIO0
SO/SIO1
Mode3
Mode0
012345678
19 20 21 22 23 24 27 28 31
8CLK
BBh
MSB
High Impedance
Add1:A22,A20-A2,A0
dummy
bit
N
N+1 N+2
X
DATA0 DATA0 DATA0 ^DATA0
b6,b4,b2,b0
12CLK
2CLK 2CLK
4CLK
Add2:A23,A21-A3,A1 X
DATA1 DATA1 DATA1 ^DATA1
b7,b5,b3,b1
MSB MSB MSB
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding
data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address
(FFFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic
level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO
is in a high-impedance state.
No.A2199-6/22