CS8122 Datasheet, PDF (6/10 Pages) Cherry Semiconductor Corporation – 2% 5V, 750mA Low Dropout Linear Regulator with Delayed RESET

V_OUT
V_RT(ON)
V_RT(OFF)
V_RH
CS8122
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0 V)
RESET
(3)
V_RL
DELAY
V_DC(HI)
V_DC(LO)
V_DH
(1)
(2)
t_DELAY
(2)
V_DIS
Figure 12. RESET Circuit Waveform
CIRCUIT DESCRIPTION
The CS8122 RESET function, has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1.0 V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram on page 2).
Low Voltage Inhibit Circuit
The Low Voltage Inhibit Circuit monitors output voltage,
and when output voltage is below the specified minimum,
causes the RESET output transistor to be in the ON
(saturation) state. When the output voltage is above the
specified level, this circuit permits the RESET output
transistor to go into the OFF state if allowed by the RESET
Delay circuit.
Reset Delay Circuit
The Reset Delay Circuit provides a programmable (by
external capacitor) delay on the RESET output lead. The
Delay lead provides source current to the external delay
capacitor only when the Low Voltage Inhibit circuit
indicates that output voltage is above V_RT(ON). Otherwise,
the Delay lead sinks current to ground (used to discharge the
delay capacitor). The discharge current is latched ON when
the output voltage is below V_RT(OFF). The Delay capacitor
is fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures that a controlled RESET pulse is generated
following detection of an error condition. The circuit allows
the RESET output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
V_DC(HI).
C_IN*
100 nF
C_Delay
0.1 mF
V_IN
V_OUT
CS8122
RESET
Delay
GND
R_RST
4.7 kW
C_OUT**
10 mF
*C_IN is required if regulator is far from the power source filter.
**C_OUT is required for stability.
Figure 13. Test Circuit
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