CS2844 Datasheet, PDF (6/12 Pages) Cherry Semiconductor Corporation – Current Mode PWM Control Circuit with 50% Max Duty Cycle

CS2844, CS3844, CS2845, CS3845
CIRCUIT DESCRIPTION
V_CC
ON/OFF Command
to reset of IC
V_ON
V_OFF
CSX844
16 V
10 V
CSX845
8.4 V
7.6 V
I_CC
< 15 mA
< 1.0 mA
V_ON V_OFF
V_CC
Figure 3. Startup Voltage for CSX844 and CSX845
Undervoltage Lockout
During Undervoltage Lockout (Figure 3), the output
driver is biased to sink minor amounts of current. The output
should be shunted to ground with a resistor to prevent
activating the power switch with extraneous leakage
currents.
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure
4). An increase in V_CC causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed–forward characteristic of current mode control, since
the control voltage does not have to change during changes
of input supply voltage.
V_OSC
OSC
RESET
Toggle
F/F Output
EA Output
Switch
Current
V_CC
I_O
V_upper
V_lower
t_on
t_off
t_d
t_c
t_on = t_c
t_off = t_c + 2t_d
Figure 5. Duty Cycle Parameters
When the power supply sees a sudden large output current
increase, the control voltage will increase allowing the duty
cycle to momentarily increase. Since the duty cycle tends to
exceed the maximum allowed to prevent transformer
saturation in some power supplies, the internal oscillator
waveform provides the maximum duty cycle clamp as
programmed by the selection of OSC components.
Setting the Oscillator
The times t_c and t_d can be determined as follows:
ǒ Ǔ tc + RTCT ln
VREF * Vlower
VREF * Vupper
ǒ Ǔ td + RTCT
ln
VREF * IdRT * Vlower
VREF * IdRT * Vupper
Substituting in typical values for the parameters in the
above formulas:
V_REF = 5.0 V, V_upper = 2.7 V, V_lower = 1.0 V, I_d = 8.3 mA
then:
tc [ 0.5534RTCT
ǒ Ǔ td + RTCT
ln
2.3 * 0.0083RT
4.0 * 0.0083RT
For better accuracy R_T should be ≥ 10 kΩ.
Grounding
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to Gnd in a
single point ground.
The transistor and 5.0 kΩ potentiometer are used to
sample the oscillator waveform and apply an adjustable
ramp to Sense.
V_O
Figure 4. Timing Diagram
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