CAV93C66 Datasheet, PDF (6/10 Pages) ON Semiconductor – 4 Kb Microwire Serial CMOS EEPROM

CAV93C66
Write
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t_CSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAV93C66 can
be determined by selecting the device and polling the DO
pin. Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t_CSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAV93C66 can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
SK
CS
STANDBY
DI
1 00
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
SK
CS
A_N A_N−1
DI
101
t_CSMIN
A₀ D_N
D₀
STATUS
VERIFY
STANDBY
t_SV
BUSY
t_HZ
DO
HIGH−Z
READY
HIGH−Z
t_EW
Figure 5. Write Instruction Timing
SK
CS
A_N A_N−1
DI
11 1
A₀
t_CS
STATUS
VERIFY
STANDBY
t_SV
t_HZ
DO
HIGH−Z
BUSY
READY HIGH−Z
t_EW
Figure 6. Erase Instruction Timing
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