CAV25512H Datasheet, PDF (6/12 Pages) ON Semiconductor – 512-Kb SPI Serial CMOS EEPROM

CAV25512H
WRITE OPERATIONS
The CAV25512H device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAV25512H. Care must be taken to take
the CS input high after the WREN instruction, as otherwise
the Write Enable Latch will not be properly set. WREN
timing is illustrated in Figure 3. The WREN instruction must
be sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
SI
0 0 0 00 1 10
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
Figure 3. WREN Timing
CS
SCK
SI
SO
Dashed Line = mode (1, 1)
00 0 0 0 1 00
HIGH IMPEDANCE
Figure 4. WRDI Timing
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