TCP-3027HA Datasheet, PDF (5/7 Pages) ON Semiconductor – Passive Tunable Integrated Circuits

TCP−3027HA
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro-static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1A sensitive.
The proper ESD handling procedures should be used.
Mounting
The QFN PTIC is fabricated for Flip Chip solder
mounting. The output pads are plated with pure tin, and the
device is rated as MSL2. The PTIC QFN is RoHS-compliant
and compatible with lead-free soldering profile.
Table 4. Reflow Profile Chart
Profile Feature
Average ramp−up rate (Ts_max to T_p)
Preheat
Temperature Min (Ts_min)
Temperature Max (Ts_max)
Time (Ts_min to Ts_max) (ts)
Time maintained above
Temperature (T_L)
Time (t_L)
Peak Temperature (Tp)
Pb−Free Assembly
3°C / second max
150°C
200°C
60−180 seconds
217°C
60−150 seconds
260°C (maximum for
the customer)
Time within 5°C of actual Peak
Temperature (tp)²
20−40 seconds
Ramp−down Rate
Time 25°C to Peak Temperature
6°C / second max
8 minutes max
Figure 6. Reflow Profile
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2 is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2 connected to RF ground.
RF
RF1
(PTIC Pad)
RF2
(PTIC Pad)
ANT
Bias
Figure 7. PTIC Orientation Functional Block
Diagram
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