PACDN009_11 Datasheet, PDF (5/7 Pages) ON Semiconductor – 5-Channel ESD Protection Array

PACDN009
the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be
slightly higher than the maximum supply voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V_P pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Notes AP209, “Design Considerations for ESD Protection” and AP219, “ESD
Protection for USB 2.0 Systems”.
L₂
V_P
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE I_ESD
ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ _D1
ÇÇÇÇÇÇ ÇÇÇÇÇÇ _ONE
ÇÇÇÇÇÇ ÇÇÇÇÇÇ D₂
CHANNEL
OF
ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ ^PACDN009
L₁
CHANNEL
INPUT
20 A
LINE BEING
PROTECTED
V_CL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
0A
V_N
GROUND RAIL
CHASSIS GROUND
Figure 2. Application of Positive ESD Pulse between Input Channel and Ground
http://onsemi.com
5