NSS20500UW3T2G_07 Datasheet, PDF (5/6 Pages) ON Semiconductor – 20 V, 7.0 A, Low VCE(sat) PNP Transistor

NSS20500UW3T2G
PACKAGE DIMENSIONS
WDFN3
CASE 506AU−01
ISSUE O
D
A
B
PIN ONE
REFERENCE
2X _{0.10 C} ^{ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ}
E
2X
0.10 C
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
MILLIMETERS
DIM MIN
NOM MAX
A 0.70
0.75
0.80
A1 0.00
0.05
A3
0.20 REF
b
0.25
0.30
0.35
D
2.00 BSC
D2 1.40
1.50
1.60
E
2.00 BSC
E2 0.90
1.00
1.10
e
1.30 BSC
K
0.35 REF
L
0.35
0.40
0.45
MIN
0.028
0.000
0.010
0.055
0.035
0.014
INCHES
NOM
0.030
0.008 REF
0.012
0.079 BSC
0.059
0.079 BSC
0.039
0.051 BSC
0.014 REF
0.016
MAX
0.031
0.002
0.014
0.063
0.043
0.018
0.10 C
8X
0.08 C
SEATING
A1
PLANE
1
2X L
SIDE VIEW
D2
e
A
(A3)
C
e/2
2
K
SOLDERING FOOTPRINT*
2X 0.400
1.300
0.250
0.600
1.100
0.300
0.400
1.600
0.275
E2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
3
3X b
BOTTOM VIEW
0.10 C A B
0.05 C NOTE 3
http://onsemi.com
5