NLSX4373 Datasheet, PDF (5/12 Pages) ON Semiconductor – 2-Bit 20 Mb/s Dual-Supply Level Translator

NLSX4373
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, C_LOAD = 15 pF, driver output impedance v 50 W, R_LOAD = 1 MW)
−405C to +855C
(Notes 3 and 4)
Symbol
Parameter
V_L = 1.5 V, V_CC = 5.5 V
t_RVCC I/O V_CC Risetime
t_FVCC I/O V_CC Falltime
t_RVL
I/O V_L Risetime
t_FVL
I/O V_L Falltime
t_{PDVL−VCC} Propagation Delay (Driving I/O V_L)
t_{PDVCC−VL} Propagation Delay (Driving I/O V_CC)
t_PPSKEW Part−to−Part Skew
Maximum Data Rate
Test Conditions
Min
Typ
Max Unit
15 ns
20 ns
30 ns
10 ns
20 ns
20 ns
5 nS
20
Mb/s
V_L = 1.8 V, V_CC = 2.8 V
t_RVCC I/O V_CC Risetime
t_FVCC I/O V_CC Falltime
t_RVL
I/O V_L Risetime
t_FVL
I/O V_L Falltime
t_{PDVL−VCC} Propagation Delay (Driving I/O V_L)
t_{PDVCC−VL} Propagation Delay (Driving I/O V_CC)
t_PPSKEW Part−to−Part Skew
Maximum Data Rate
15 ns
15 ns
25 ns
10 ns
15 ns
15 ns
5 nS
20
Mb/s
V_L = 2.5 V, V_CC = 3.6 V
t_RVCC I/O V_CC Risetime
t_FVCC I/O V_CC Falltime
t_RVL
I/O V_L Risetime
t_FVL
I/O V_L Falltime
t_{PDVL−VCC} Propagation Delay (Driving I/O V_L)
t_{PDVCC−VL} Propagation Delay (Driving I/O V_CC)
t_PPSKEW Part−to−Part Skew
Maximum Data Rate
15 ns
10 ns
15 ns
10 ns
15 ns
15 ns
5 nS
20
Mb/s
V_L = 2.8 V, V_CC = 1.8 V
t_RVCC I/O V_CC Risetime
t_FVCC I/O V_CC Falltime
t_RVL
I/O V_L Risetime
t_FVL
I/O V_L Falltime
t_{PDVL−VCC} Propagation Delay (Driving I/O V_L)
t_{PDVCC−VL} Propagation Delay (Driving I/O V_CC)
t_PPSKEW Part−to−Part Skew
Maximum Data Rate
25 ns
10 ns
20 ns
15 ns
15 ns
15 ns
5 nS
20
Mb/s
3. Typical values are for V_CC = +3.3 V, V_L = +1.8 V and T_A = +25°C.
4. All units are production tested at T_A = +25°C. Limits over the operating temperature range are guaranteed by design.
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