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NCP3488 Datasheet, PDF (5/7 Pages) ON Semiconductor – MOSFET Driver with Dual Outputs for Synchronous Buck Converters | |||
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OD
DRVH
or
DRVL
NCP3488
tpdlOD
90%
tpdhOD
10%
Figure 2. Output Disable Timing Diagram
IN
DRVL
DRVHâSW
SW
tpdlDRVL
tfDRVL
90%
2V
10%
tpdhDRVH
trDRVH
90%
10%
90%
tpdlDRVH
tfDRVH
90%
10%
trDRVL
2V 10%
tpdhDRVL
Figure 3. Nonoverlap Timing Diagram
APPLICATIONS INFORMATION
Theory of Operation
The NCP3488 is a single phase MOSFET driver designed
for driving two Nâchannel MOSFETs in a synchronous buck
converter topology. The NCP3488 will operate from 5 V or
12 V, but it has been optimized for high current multiâphase
buck regulators that convert 12 Volt rail directly to the core
voltage required by complex logic chips. A single PWM input
signal is all that is required to properly drive the highâside and
the lowâside MOSFETs. Each driver is capable of driving a
3.3 nF load at frequencies up to 500 kHz.
LowâSide Driver
The lowâside driver is designed to drive a
groundâreferenced low RDS(on) NâChannel MOSFET. The
voltage rail for the lowâside driver is internally connected to
the VCC supply and PGND.
HighâSide Driver
The highâside driver is designed to drive a floating low
RDS(on) Nâchannel MOSFET. The gate voltage for the high
side driver is developed by a bootstrap circuit referenced to
Switch Node (SW) pin.
The bootstrap circuit is comprised of an external diode,
and an external bootstrap capacitor. When the NCP3488 is
starting up, the SW pin is at ground, so the bootstrap
capacitor will charge up to VCC through the bootstrap diode
See Figure 4. When the PWM input goes high, the highâside
driver will begin to turn on the highâside MOSFET using the
stored charge of the bootstrap capacitor. As the highâside
MOSFET turns on, the SW pin will rise. When the highâside
MOSFET is fully on, the switch node will be at 12 volts, and
the BST pin will be at 12 volts plus the charge of the
bootstrap capacitor (approaching 24 volts).
The bootstrap capacitor is recharged when the switch
node goes low during the next cycle.
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