NCP1082 Datasheet, PDF (5/16 Pages) ON Semiconductor – Integrated PoE-PD & DC-DC Converter Controller with 9V Auxiliary Supply Support

NCP1082
Table 1. Pin Descriptions
Name
Pin No.
Type
VPORTP
1
Supply
VPORTN1
6,8
VPORTN2
Ground
RTN
7
Ground
ARTN
14
Ground
VDDH
16
Supply
VDDL
17
Supply
CLASS
2
INRUSH
4
ILIM1
5
Input
Input
Input
UVLO
3
Input
GATE
OSC
NC
COMP
15
Output
11
Input
13
18
I/O
FB
CS
SS
AUX
19
Input
12
Input
20
Input
9
Input
TEST
EP
10
Input
Description
Positive input power. Voltage with respect to VPORTN_1,2
Negative input power. Connected to the source of the internal pass−switch.
DC−DC controller power return. Connected to the drain of the internal pass−switch. It must
be connected to ARTN. This pin is also the drain of the internal pass−switch.
DC−DC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with
low ESR.
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external low−power LED (1 mA max.) connected to ARTN, and can also be
used to add extra biasing current in the external opto−coupler. VDDL must be bypassed to
ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
Classification current programming pin. Connect a resistor between CLASS and VPORTN_1,2.
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN_1,2.
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN_1,2.
DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN_1,2. Connect
a resistor−divider from VPORTP to UVLO to VPORTN_1,2 to set an external UVLO threshold.
DC−DC controller gate driver output pin.
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
No connect pin, must not be connected.
Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
opto−coupler. Voltage with respect to ARTN.
DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
Current−sense input for the DC−DC controller. Voltage with respect to ARTN.
Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the
soft−start timing.
When the pin is pulled up, the IEEE detection mode is disabled and the device can be sup-
plied by an auxiliary supply. Voltage with respect to VPORTN_1,2. Connect the pin to the auxili-
ary supply through a resistor divider.
Digital test pin must always be connected to VPORTN_1,2.
Exposed pad. Connected to VPORTN_1,2 ground.
http://onsemi.com
5