NB4N7132_11 Datasheet, PDF (5/6 Pages) ON Semiconductor – Link Replicator for Fibre Channel, Gigabit Ethernet HDTV and SATA

NB4N7132
0.01mF
TX+
I+
R
0.01mF
RT
TX−
I−
R
0.01mF
O1+
I1+
0.01mF ^RT
O1−
I1−
0.01mF
O+
RX+
0.01mF
RT
O−
RX−
SerDes
RX+
RX−
0.01mF
RT
0.01mF
NB4N7132
O+
I1+
O−
I1−
0.01mF
RT
0.01mF
NB4N7132
O1+
I+
O1−
I−
0.01mF
RT
0.01mF
SerDes
TX+
R
TX−
R
“R” is 150 W for both 100 W differential or 150 W differential traces.
“RT” matches the differential impedance of the link.
Figure 5. NB4N7132 Application Interface Example
IN+/IN− Input Functionality
The differential inputs are internally biased to Y1.2 V. In
a typical application, the differential inputs are
capacitor−coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N7132 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
OUT+ / OUT− Outputs
The OUT+ and OUT− outputs of the NB4N7132 are
designed to drive differential transmission lines with
nominally 50 W or 75 W characteristic impedance. These
differential output buffers utilize positive emitter coupled
logic (PECL) architecture, but they do not require DC output
load resistors, and will operate properly with or without the
resistors.
OEx Output Enable
The NB4N7132 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in I_DD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx− are set HIGH.
Power Supply Bypass information
A clean power supply will optimize the performance of
the device. The NB4N7132 provides separate power supply
pins for the digital circuitry (V_DD) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01 mF to 0.1 mF
on each VDD pin will help ensure a noise free V_DD power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Resource Reference of Application Notes
AND8002 − Marking and Date Codes
AND8009 − ECLinPS Plus Spice I/O Model Kit
ORDERING INFORMATION
Device
Package
Shipping^†
NB4N7132DTG
TSSOP−28
(Pb−Free)
50 Units / Rail
NB4N7132DTR2G
TSSOP−28
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
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