N04L63W1A Datasheet, PDF (5/10 Pages) ON Semiconductor – 4Mb Ultra-Low Power Asynchronous CMOS SRAM 256K × 16 bit

N04L63W1A
Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature
0.1V_CC to 0.9 V_CC
5ns
0.5 V_CC
CL = 30pF
-40 to +85 ^oC
Timing
Item
Symbol
Read Cycle Time
Address Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
t_RC
t_AA
t_CO
t_OE
t_LB, t_UB
t_LZ
t_OLZ
t_BZ
t_HZ
t_OHZ
t_BHZ
t_OH
-70
2.3 - 2.65 V
2.7 - 3.6 V
Min. Max. Min. Max.
85
70
85
70
85
70
30
25
85
70
10
10
5
5
10
10
0
20
0
20
0
20
0
20
0
20
0
20
10
10
-55
2.7 - 3.6 V
Min. Max.
55
55
55
25
55
10
5
10
0
20
0
20
0
20
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
t_WC
85
70
55
ns
Chip Enable to End of Write
t_CW
50
50
45
ns
Address Valid to End of Write
t_AW
50
50
45
ns
Byte Select to End of Write
t_BW
50
50
45
ns
Write Pulse Width
t_WP
40
40
40
ns
Address Setup Time
t_AS
0
0
0
ns
Write Recovery Time
t_WR
0
0
0
ns
Write to High-Z Output
t_WHZ
20
20
20
ns
Data to Write Time Overlap
t_DW
40
40
40
ns
Data Hold from Write Time
t_DH
0
0
0
ns
End Write to Low-Z Output
t_OW
5
5
5
ns
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