MC74HCT595ADG Datasheet, PDF (5/11 Pages) ON Semiconductor – 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs and LSTTL Compatible Inputs

MC74HCT595A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Symbol
Parameter
f_max Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
t_PLH,
t_PHL
t_PHL
Maximum Propagation Delay, Shift Clock to SQ_H
(Figures 1 and 7)
Maximum Propagation Delay, Reset to SQ_H
(Figures 2 and 7)
t_PLH,
t_PHL
t_PLZ,
t_PHZ
t_PZL,
t_PZH
t_TLH,
t_THL
t_TLH,
t_THL
C_in
C_out
Maximum Propagation Delay, Latch Clock to Q_A − Q_H
(Figures 3 and 7)
Maximum Propagation Delay, Output Enable to Q_A − Q_H
(Figures 4 and 8)
Maximum Propagation Delay, Output Enable to Q_A − Q_H
(Figures 4 and 8)
Maximum Output Transition Time, Q_A − Q_H
(Figures 3 and 7)
Maximum Output Transition Time, SQ_H
(Figures 1 and 7)
Maximum Input Capacitance
Maximum Three−State Output Capacitance (Output in
High−Impedance State), Q_A − Q_H
V_CC
V
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
—
—
Guaranteed Limit
– 55 to 25_C v 85_C v 125_C
30
24
20
28
35
42
29
36
44
28
35
42
30
38
45
27
34
41
12
15
18
15
19
22
10
10
10
15
15
15
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
pF
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Package)*
300
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
TIMING REQUIREMENTS (Input t_r = t_f = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tsu Minimum Setup Time, Shift Clock to Latch Clock}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Figure 6)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _th
Minimum Hold Time, Shift Clock to Serial Data Input A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 5)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ trec Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
Minimum Pulse Width, Reset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Figure 2)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
Minimum Pulse Width, Shift Clock
(Figure 1)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
Minimum Pulse Width, Latch Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Figure 6)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tr, tf Maximum Input Rise and Fall Times}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)
Guaranteed Limit
V_CC
V 25_C to –55_C v 85_C v 125_C Unit
4.5 to
10
5.5
13
15
ns
4.5 to
15
5.5
19
22
ns
4.5 to
5.0
5.5
5.0
5.0
ns
4.5 to
10
5.5
13
15
ns
4.5 to
12
5.5
15
18
ns
4.5 to
10
5.5
13
15
ns
4.5 to
10
5.5
13
15
ns
4.5 to
500
5.5
500
500
ns
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