MC74HC597A Datasheet, PDF (5/12 Pages) ON Semiconductor – 8-Bit Serial or Parallel- Input/Serial-Output Shift Register

MC74HC597A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6 ns)
Symbol
f_max
Parameter
Maximum Clock Frequency (50% Duty Cycle), Shift Clock
(Figures 4 and 10)
t_PLH,
t_PHL
Maximum Propagation Delay, Latch Clock to Q_H
(Figures 3 and 10)
t_PLH,
t_PHL
Maximum Propagation Delay, Shift Clock to Q_H
(Figures 4 and 10)
t_PHL
Maximum Propagation Delay, Reset to Q_H
(Figures 5 and 10)
t_PLH,
t_PHL
Maximum Propagation Delay, Serial Shift/Parallel Load to Q_H
(Figures 6 and 10)
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 3 and 10)
C_in
Maximum Input Capacitance
Guaranteed Limit
V_CC
– 55 to
V
25_C v 85_C v 125_C _Unit
2.0
10
9
8
MHz
3.0
15
14
12
4.5
30
28
25
6.0
50
45
40
2.0
175
225
275
ns
3.0
100
110
125
4.5
40
50
60
6.0
30
40
50
2.0
160
200
240
ns
3.0
90
130
160
4.5
30
40
48
6.0
25
30
40
2.0
160
200
240
ns
3.0
90
130
160
4.5
30
40
48
6.0
25
30
40
2.0
160
200
240
ns
3.0
90
130
160
4.5
30
40
48
6.0
25
30
40
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
—
10
10
10
pF
Typical @ 25°C, V_CC = 5.0 V
C_PD
Power Dissipation Capacitance (Per Package)*
40
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
S_A (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
Reset (Pin 10)
Asynchronous, Active−low shift register reset. A low level
applied to this input resets the shift register to a low level,
but does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A low−to−high transition on this
input shifts data on the Serial Data Input into the shift
register and data in stage H is shifted out Q_H, being
replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
Latch clock. A low−to−high transition on this input loads
the parallel data on inputs A−H into the input latch.
OUTPUT
Q_H (Pin 9)
Serial data output. This pin is the output from the last
stage of the shift register.
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