MC74HC4060A Datasheet, PDF (5/12 Pages) ON Semiconductor – 14-Stage Binary Ripple Counter With Oscillator

MC74HC4060A
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative–edge triggering clock input. A high–to–low
transition on this input advances the state of the counter. Osc
In may be driven by an external clock source.
Reset (Pin 12)
Active–high reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.
OUTPUTS
Q4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction
with Osc In and the external components to form an
oscillator. When Osc In is being driven with an external
clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in Figure
6, Osc Out 2 must be left open circuited.
SWITCHING WAVEFORMS
tf
tr
90%
VCC
Osc In
50%
10%
GND
tw
1/fMAX
tPLH
tPHL
90%
Q _50%
10%
tTLH
tTHL
Figure 1.
Reset
Q
tw
50%
tPHL
50%
Osc In
Figure 2.
VCC
GND
trec
VCC
50%
GND
Qn
50%
tPLH
VCC
GND
tPHL
Qn+1
50%
Figure 3.
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
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