MC74HC244A_06 Datasheet, PDF (5/8 Pages) ON Semiconductor – Octal 3−State Noninverting Buffer/Line Driver/ Line Receiver High−Performance Silicon−Gate CMOS

DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 3. Test Circuit
MC74HC244A
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
C_L*
CONNECT TO V_CC WHEN
TESTING t_PLZ AND t_PZL.
CONNECT TO GND WHEN
TESTING t_PHZ AND t_PZH.
*Includes all probe and jig capacitance
Figure 4. Test Circuit
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
Enable A, Enable B (Pins 1, 19)
Output enables (active−low). When a low level is applied
to these pins, the outputs are enabled and the devices
function as noninverting buffers. When a high level is
applied, the outputs assume the high impedance state.
OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
Device outputs. Depending upon the state of the
output−enable pins, these outputs are either noninverting
outputs or high−impedance outputs.
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS
DATA
INPUT
A OR B
ONE OF 8
INVERTERS
V_CC
YA
OR
YB
ENABLE A OR
ENABLE B
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