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MC74HC161A_13 Datasheet, PDF (5/15 Pages) ON Semiconductor – Presettable Counters
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MC74HC161A, MC74HC163A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Guaranteed Limit
VCC
Figure V – 55 to 25_C v 85_C v 125_C Unit
fmax Maximum Clock Frequency
(50% Duty Cycle)
(Note 6)
4, 10 2.0
6
3.0
15
4.5
30
6.0
35
5
4
MHz
12
10
24
20
28
24
tPLH Maximum Propagation Delay,
Clock to Q
4, 10 2.0
120
3.0
75
4.5
20
6.0
16
160
200
ns
120
150
23
28
20
22
tPHL
4, 10 2.0
145
185
220
ns
3.0
100
135
150
4.5
22
25
30
6.0
18
20
23
tPHL Maximum Propagation Delay,
Reset to Q (HC161A Only)
5, 10 2.0
145
3.0
100
4.5
20
6.0
17
185
220
ns
135
150
22
25
19
21
tPLH Maximum Propagation Delay,
Enable T to Ripple Carry Out
6, 10 2.0
110
3.0
60
4.5
16
6.0
14
150
190
ns
115
140
18
20
15
17
tPHL
6, 10 2.0
135
175
210
ns
3.0
100
130
160
4.5
18
20
22
6.0
15
16
20
tPLH Maximum Propagation Delay,
Clock to Ripple Carry Out
4, 10 2.0
120
3.0
75
4.5
22
6.0
18
160
200
ns
135
150
27
30
22
25
tPHL
4, 10 2.0
145
185
220
ns
3.0
100
135
150
4.5
22
28
35
6.0
20
24
28
tPHL Maximum Propagation Delay,
Reset to Ripple Carry Out
(HC161A Only)
5, 10 2.0
155
3.0
120
4.5
22
6.0
18
190
230
ns
140
155
26
30
22
25
tTLH,
tTHL
Maximum Output Transition Time,
Any Output
5, 10 2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
Cin
Maximum Input Capacitance
4, 10
−
10
10
10
pF
6. Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.
See Applications information in this data sheet.
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate) (Note 7)
45
pF
7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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