MC1496_06 Datasheet, PDF (5/14 Pages) ON Semiconductor – Balanced Modulators/Demodulators

MC1496, MC1496B
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.
Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
⎥ g_21C⁺
io
(each sideband)
vs (signal)
Vo + 0
Signal transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
⎥ g_21S⁺
io
vs
(signal)
(signal)
Vc + 0.5 Vdc, Vo + 0
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 W at the carrier frequency.
Output Signal
The output signal is taken from Pins 6 and 12 either
balanced or single−ended. Figure 11 shows the output levels
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single−ended output connection.
Negative Supply
V_EE should be dc only. The insertion of an RF choke in
series with V_EE can enhance the stability of the internal
current sources.
Signal Port Stability
Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the source−tuned
circuits that cause the oscillation.
Signal Input
(Pins 1 and 4)
510
10 pF
An alternate method for low−frequency applications is to
insert a 1.0 kW resistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation
of carrier suppression.
TEST CIRCUITS
V_CC
12 Vdc
1.0 k
1.0 k
R_e = 1.0 k
Carrier
Input
C₂
0.1 mF
V_C
V_S
Modulating
Signal Input _{10 k}
51
C1
0.1 mF
10 k 51
R_e
R_L
R_L
8 ^{2 1.0 k 3 3.9 k}
3.9 k
10
1 MC1496
6
I9 I6
+V _o
4
12
−V _o
51
14
5
50 k
R1
Carrier Null
I10 ^{I5 6.8 k}
V^−
−8.0 Vdc
V_EE
Figure 5. Carrier Rejection and Suppression
2
3
0.5 V 8
+ − ₁₀
1 MC1496 ⁶
Z_in
4
12
14
5
6.8 k
+V
Z_out
o
−V _o
−8.0 Vdc
NOTE: Shielding of input and output leads may be needed
to properly perform these tests.
Figure 6. Input−Output Impedance
1.0 k
I7
I8
1.0 k I1
I4
V_CC
12 Vdc
R_e = 1.0 k
2
8
3
2.0 k
I6
10
1 ^{MC1496 6 I9}
4
12
14
5
I10 _{6.8 k}
−8.0 Vdc
V_EE
Figure 7. Bias and Offset Currents
V_CC
1.0 k
1.0 k
12 Vdc
Carrier
Input ^{0.1 mF}
V_C
V_S
Modulating
Signal Input
10 k
R_e
2.0 k
51 _{0.1 mF}
1.0 k
82
3
0.01
50 50 ^mF
10
1 MC1496 ⁶
4
12
+V _o
−V _o
10 k 51 51
14
5
50 k
6.8 k
Carrier Null
V^−
−8.0 Vdc
V_EE
Figure 8. Transconductance Bandwidth
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